| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 賴弼廷 | zh_TW |
| DC.creator | Bi-Ting Lai | en_US |
| dc.date.accessioned | 2011-8-15T07:39:07Z | |
| dc.date.available | 2011-8-15T07:39:07Z | |
| dc.date.issued | 2011 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=985201026 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 隨著製程的演進，積體電路的元件尺寸逐漸縮小，已經達到32 奈米製程。由於可印刷性和可製造性的問題，微影技術（lithography）遇到了瓶頸。雙圖案微影技術（double patterning lithography）被視為近來最適合改善32 奈米製程以下的技術。
雙圖案微影技術是基於目前的製程技術下，將每一層的整體佈局分解為兩個光罩以加大最小圖案間距和改善焦距深度。當發生圖案衝突（conflict）時，即遇到整體佈局無法被完整地分解為兩個光罩，就必須把單一佈局圖案切割成兩個次圖案，此分割動作造成同一個佈局圖案被分解到不同光罩而產生需要接合，我們稱此接合處為縫合圖案（stitch）。假如晶片平面上沒有足夠的空間插入縫合圖案以解決衝突，即產生了原生衝突（native conflict），此時，便需要曠日費時地進行佈局修正。目前的相關研究多著重在後佈局（post layout）階段或細部繞線（detailed routing）階段以降低縫合圖案和原生衝突的數目，然而隨著現今佈局的複雜度愈來愈高，如何在繞線階段提早考量雙圖案微影技術且不會增加細部繞線的負擔，將是一大挑戰。
本論文提出在軌道繞線（track routing）階段考量雙圖案微影技術。我們提出的方法不僅可以有效地降低原生衝突的數量，還可以加速後續細部繞線的處理時間。此外，我們提出虛擬節點（pseudo pin）的技術，不只可以在軌道繞線時避免大量的原生衝突，還可粗略地估計細部繞線的走向，幫助軌道繞線找出合適的繞線軌道以達到最短繞線路徑的目的。實驗結果顯示，本論文提出的方法在微幅增加繞線線長下，可大量地降低原生衝突數量，同時更可提高繞線的完成度。
| zh_TW |
| dc.description.abstract | As the manufacturing process advances, the size of integrated circuits has shrunk into the 32 nm. Lithography process encounters a bottleneck due to printability and manufacturability issues. Recently, double patterning lithography（DPL）has been proposed for the most feasible solution for sub-32-nm node process.
To increase the half-pitch resolution and improve depth of focus, DPL decomposes a layout into two masks by using current infrastructures. The conflict of DPL means that a layout cannot be decomposed completely, and then the un-decomposable pattern must be partitioned into two sub-patterns. These two sub-patterns should be assigned to different masks and connected to each other. The touching edge of sub-patterns is called stitch. If there is no enough space to insert a stitch for the un-decomposable pattern, a native conflict is generated. A layout with native conflicts will result in layout modification. The current researches focus on reducing the number of stitches and the number of native conflicts in the post layout phase or detailed routing phase. Since the layout is more and more complicated, considering DPL before detailed routing and alleviating the loading in detailed routing will be a challenge.
In this thesis, we propose a method to consider DPL in track routing. Besides, we propose a pseudo pin technique to avoid generating a lot of native conflicts in track routing and predict the traces of detailed routing. Experimental results show that the proposed method not only minimizes the number of native conflicts significantly, but also reduces wirelength.
| en_US |
| DC.subject | 軌道繞線 | zh_TW |
| DC.subject | 雙圖案微影技術 | zh_TW |
| DC.subject | double patterning technology | en_US |
| DC.subject | track routing | en_US |
| DC.title | 雙圖案微影技術下考慮原生衝突之電路軌道繞線 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Native-Conflict-Aware Track Routing for Double Patterning Technology | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |