| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 沙宇杰 | zh_TW |
| DC.creator | Yu-Jie Sha | en_US |
| dc.date.accessioned | 2011-11-24T07:39:07Z | |
| dc.date.available | 2011-11-24T07:39:07Z | |
| dc.date.issued | 2011 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=985201028 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 在日常生活的娛樂與通訊中，數位音訊編碼扮演著一個很重要的角色。自從MPEG Layer-III（MP3）被發佈出來並且在3C產品中變成非常有名，MPEG協會提出了MPEG-2 Advanced Audio Coding（AAC）為新一代的音訊編碼規格。在這個新的規格中，它的性能與壓縮率都比MP3要來的高。可是它的演算法也相對來說更複雜而且包含更高的運算量。因此如何降低AAC編碼器的運算量並且維持低失真率是一個主要的挑戰。
在本論文中，我們提出了一個MPEG-2 AAC編碼器的SoC設計，而且針對MPEG-2 AAC編碼器中最主要的組件做最佳化，也就是聲學模型（PAM）。為了要減少聲學模型的複雜度，我們使用了基於改良式離散餘弦轉換之聲學模型（MDCT-based PAM）來減輕整個系統的運算量。我們使用台積電的0.18μm 1P6M CMOS製程來實現我們所提出的編碼器。為了增加我們所設計的硬體加速器的處理能力（throughput），我們使用了管線與摺疊式的設計。本設計的總邏輯閘數是284K個，而基於改良式離散餘弦轉換之聲學模型與Andes Core N903處理器針對取樣頻率為44100赫茲、立體聲道的音樂可以達到即時編碼，其所需的操作頻率各為10兆赫與100兆赫。
| zh_TW |
| dc.description.abstract | Digital audio coding has played an important role in our daily life for entertainment and communication. Since MPEG Layer-III (MP3) had been published, and became very popular in consumer applications, the MPEG organization proposed MPEG-2 Advanced Audio Coding (AAC) standard as the next generation of audio standard. Both performance and compression ratio of AAC are better than MP3. However, the algorithm is more complex and computation-intensive. Thus, how to reduce the computation and maintain the audio fidelity is the major challenge of AAC encoder.
In this thesis, we proposed an SoC design of MPEG-2 AAC encoder, and optimized the key component of MPEG-2 AAC encoder, which is the psychoacoustic model (PAM). In order to reduce the complexity of psychoacoustic model, we used the MDCT-based PAM to alleviate the loading of the entire system. Our proposed encoder is implemented in TSMC 0.18 μm 1P6M CMOS technology. Pipelining and folding technique are used to increase throughput of the hardware accelerator. The total gate count is 284K and the operating frequency for real-time stereo channel of sampling rate 44.1KHz audio sequence processing is 10 MHz and 100MHz for MDCT-based PAM and Andes Core N903 processor respectively.
| en_US |
| DC.subject | SoC | zh_TW |
| DC.subject | MDCT | zh_TW |
| DC.subject | Encoder | zh_TW |
| DC.subject | AAC | zh_TW |
| DC.subject | SoC | en_US |
| DC.subject | Encoder | en_US |
| DC.subject | MDCT | en_US |
| DC.subject | AAC | en_US |
| DC.title | MPEG-2 AAC編碼器的SoC設計 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | An SoC Design of MPEG-2 AAC Encoder | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |