博碩士論文 985201056 完整後設資料紀錄

DC 欄位 語言
DC.contributor電機工程學系zh_TW
DC.creator李明師zh_TW
DC.creatorMing-Shih Leeen_US
dc.date.accessioned2011-8-12T07:39:07Z
dc.date.available2011-8-12T07:39:07Z
dc.date.issued2011
dc.identifier.urihttp://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=985201056
dc.contributor.department電機工程學系zh_TW
DC.description國立中央大學zh_TW
DC.descriptionNational Central Universityen_US
dc.description.abstract本論文整合一維複晶矽奈米線與PIN結構於一體,實作出奈米線穿隧式場效電晶體。期望能有效地改善金氧半場效電晶體的短通道效應、次臨限斜率與靜態漏電流。其關鍵製程簡述如下:利用側壁回蝕技術在陡直的平台側壁形成一維複晶矽奈米線,再藉由二次黃光微影製程分別對一維複晶矽奈米線進行P+ 和N+ 離子佈植形成PIN結構,進而實作出奈米線穿隧式場效電晶體。因此於變溫的電流-電壓曲線、次臨限斜率-溫度曲線以及導通電流-溫度曲線進行電性分析。 zh_TW
dc.description.abstractThis thesis integrated one dimension poly-Si nanowire and PIN structure into a device, which fabricated nanowire tunneling field-effect transistor (NWT-FET). We are looking forward to improving short channel effects (SCE), subthreshold slope, (S.S.) and static leakage current (IOFF) in the metal oxide semiconductor field-effect transistor (MOS-FET). The key process of NWT-FET is described as follows: By using etched back technique, we can form one dimension poly-Si nanowire on steep mesa-sidewall. Then by using two photolithography processes, we can implant P+ and N+ on one dimension poly-Si nanowire, respectively, to form the PIN structure. Via the variable temperature measurement (300 K, 250 K, 200 K and 150 K), we experimental characterized the current-voltage (I-V), subthreshold slope-temperature (S.S.-Temp.) and on current-temperature (Ion-Temp.). en_US
DC.subject奈米線zh_TW
DC.subjectPINzh_TW
DC.subject奈米線穿隧式場效電晶體zh_TW
DC.subject次臨限斜率zh_TW
DC.subject靜態漏電流zh_TW
DC.subjectNanowireen_US
DC.subjectPINen_US
DC.subjectNanowire Tunneling Field-Effect Transistoren_US
DC.subjectSubthreshold Slopeen_US
DC.subjectStatic Leakage Currenten_US
DC.title新穎奈米線穿隧式場效電晶體之技術開發zh_TW
dc.language.isozh-TWzh-TW
DC.titleTechnology Development of Novel Naonwire Tunneling Field-Effect Transistoren_US
DC.type博碩士論文zh_TW
DC.typethesisen_US
DC.publisherNational Central Universityen_US

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