| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 張藝儒 | zh_TW |
| DC.creator | Yi-ju Chang | en_US |
| dc.date.accessioned | 2012-1-20T07:39:07Z | |
| dc.date.available | 2012-1-20T07:39:07Z | |
| dc.date.issued | 2012 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=985201109 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 在現今複雜的系統晶片(SOC)中，嵌入式記憶體是一個很重要之元件。這些系統晶片通常包含了大量的記憶體，而這些記憶體一般佔據整體系統晶片一半以上的面積，這造成記憶體良率會支配整體系統晶片之良率。因此，有效提升系統晶片中記憶體良率之技術是必須的。而記憶體內建自我修復技術(BISR)是一個已被廣泛使用於改善記憶體良率的有效技術。
一個BISR 電路通常包含一個內建備份元件分析(BIRA)電路來分配記憶體的備份元件，而BIRA 電路的效率好壞會很嚴重地影響BISR 的修復效率。論文的第一部分，針對擁有3D備份元件的大容量記憶體，提出了內建備份元件分析技術。這個技術提供了可程式化的功能，可以服務多個記憶體和支援多次測試的功能，使得可以進一步提升修復效率。實驗結果證明了這項技術可以達到很高的修復效率，針對128K-bit的記憶體，所提出的內建備份元件分析電路的面積負擔只為2.83%。
論文的第二部分，針對擁有3D 備份元件的大容量記憶體，提出了二個可以達到最佳修復效率的BIRA 技術。其中第一項技術使用了一個分析器就可以支援多個修復策略和支援字組導向記憶體執行同速測試與修復。由實驗結果觀察可知，這項技術是低面積負擔。舉例來說，針對2M-bit的記憶體有16個bank，且每個bank的大小為8192x16-bit，這個電路的面積負擔大約是0.92%。另外，為了去進一步減少面積成本，提出了一個低成本的內建備份元件分析技術，同樣可以使用一個分析器就可以支援多個修復策略，並且降低電路的面積成本，但是無法執行記憶體同速測試與修復。由實驗結果觀察可知，針對相同之記憶體，所提低成本的BIRA 電路的面積負擔大約只有0.62%。
| zh_TW |
| dc.description.abstract | In modern complex system-on-chip (SOC) designs, embedded random access memory (RAM)is a key component. A complex SOC typically contains a large number of RAM cores, and these cores usually occupy more than one half of the area of the SOC. Therefore, the yield of the SOC is dominated by the yield of RAM cores. Thus, effective yield-enhancement techniques are essential for RAM cores in SOCs. Built-in self-repair (BISR) technique has been acknowledged as one effective technique for improving the yield of embedded RAMs with redundancy.
A BISR circuit typically has a built-in redundancy-analysis (BIRA) module for allocating the redundancy. The efficiency of BIRA has heavy impact on the repair efficiency of the BISR circuit. In the first part of this thesis, we present a BIRA scheme for large RAMs with 3D redundancy (i.e., spare rows, spare columns, and spare IOs). The proposed BIRA scheme also can be designed as programmable such that it can serve multiple RAMs and support the multiple-time repair function to increase the repair rate further. Experimental results show that the proposed BISR scheme can achieve high repair rate and the area overhead of the proposed BIRA circuit for a 128K-bit RAM is only 2.83%.
In the second part of this thesis, two BIRA schemes with optimal repair rate for RAMs with 3D redundancy are proposed. One BIRA scheme using one analyzer to support multiple repair solutions is proposed to support the at-speed test and repair of word-oriented RAMs. Simulation results show that the area overhead of the proposed BIRA scheme is low. For example, the hardware overhead of the proposed BIRA circuit is about 0.92% for a 2M-bit RAM with sixteen 8192×16-bit banks. To reduce the area cost further, a low-cost parallel BIRA design using one analyzer to support multiple repair solutions is proposed as well to reduce the area cost of the BIRA circuit, but it cannot perform the test and repair of RAMs at speed. Simulation results show that the low-cost BIRA scheme can reduce the hardware overhead of the proposed BIRA circuit to about 0.62% for a 2M-bit RAM with sixteen 8192×16-bit banks.
| en_US |
| DC.subject | 記憶體修復 | zh_TW |
| DC.subject | 記憶體測試 | zh_TW |
| DC.subject | memory repair | en_US |
| DC.subject | memory test | en_US |
| DC.subject | redundancy | en_US |
| DC.subject | yield enhancement | en_US |
| DC.title | 應用於大容量隨機存取記憶體之內建備份元件分析技術 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Built-In Redundancy-Analysis Schemes for Large-Capacity RAMs | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |