dc.description.abstract | With the rapid development of semiconductor process technology, the operation frequency of the chip is much more faster than before. PLL is widely used in many communication chip systems to solve the phase error and delay of clock signal. It ensures the date be transferred correctly and provides a steady clock signal.
In terms of the PLL operation, due to the nonidealities such as the charge pump (CP) current mismatch, clock feedthrough, charge injection by the CP switches and so on. Those issues would be periodically covered to dc or ac current, which was injected into the loop filter at the input reference frequency (Fref). Accordingly, the periodic current-to-voltage integration to the control voltage leads to the voltage dithering, and converts such power to both sides of the carrier power at the reference frequency offset, which is so-called reference spur.
A 5 GHz PLL with the suppressive reference spur is presented in this work. Based on the narrowband frequency modulation approximation, it indicates that the gain of the voltage-controlled oscillator (KVCO) and Fref is directly and inversely proportional to the magnitude of the reference spur, respectively. Thus, the suppressive reference spur technique is presented in this work. This technique uses the multi-band calibration scheme to reduce the KVCO gain, as well as collaborates with the two pulse repetition (2-PR) and the four pulse position modulation (4-PPM) to duplicates the frequency of CP current pulses and randomizes such positions, respectively. With regard to the 2-PR and 4-PPM, the proposed digital phase selector (DPS) is realized for such implementation. As a result, by the use of Fref of 50 MHz, the simulated reference spur is attenuated by 78.6 dBc at the 50-MHz frequency offset from the carrier frequency of 5 GHz, and the peak-to-peak jitter is less than 3.9 ps. The chip core area occupies 0.41 mm2, and the total power consumption is around 13.7 mW at supply of 1.2V.
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