| dc.description.abstract | DVB-T2, which is an abbreviation for Digital Video Broadcasting – Second Generation Terrestrial, is a draft standard ratified by the DVB Steering Board on June 26, 2008. Compared to the original DVB-T specification, the new standard increases the channel capacity to fulfill the need for High Definition TV transmission with satisfactory error performance.
The DVB-T2 system uses multi-rate Low Density Parity Check (LDPC) codes, which are characterized by multiple parity-check matrices, as the inner encoding to provide satisfactory error performance. The optimal decoding algorithm for LDPC code, Sum-Product Algorithm, requires very complex calculation and is not favorable for hardware implementation. Therefore, we use the Modified Min-Sum Algorithm, which provide a error performance not far from the Sum-Product Algorithm, as the decoding algorithm for hardware implementation. Although the Parity-Check matrices of the multi-rate LDPC codes specified in the DVB-T2 standard do not show any Quasi-Cyclic (QC) form, they can be transformed to a QC form through specific column/row-wise cyclic permutations. In this thesis, we modify a reconfigurable hardware decoder architecture, which suitable for general QC-LDPC codes, for implementation of such multi-rate DVB-T2 LDPC decoders. The reconfiguration is simply achieved through a lookup table load with corresponding parameters. Moreover, to lower the hardware implementation complexity, we propose a bit-slice architecture with a trade off in the system throughput rate.
| en_US |