| dc.description.abstract | In this dissertation, the researches focus on the development of SOB-based 3-D network optical path for chip-level optical interconnects. The researches can be divided into three major topics, including the point-to-point 3-D optical path, the flexible 3-D network optical path with vertical power splitter and vertical transition structure, and the implementation of SOI-based chip-level optical interconnects with lasers and PDs. Using 3-D network optical path, the electronic and optical circuits can be respectively built on the rear (electronics layer) and front (optics layer) side of SOI substrate using compatible fabrication process. Because of the unique separated photonics-electronics design, active photonics devices and passive optics can be easily integrated with electronics circuits in a single silicon chip, and the high-speed data transmission with low power consumption for chip-level optical interconnects can be also achieved.
With respect to the research on the point-to-point 3-D optical path, the high-quality 45˚ micro-reflectors and crystalline silicon trapezoidal waveguides is realized on the SOI substrate using anisotropic wet-etching process. Using the 3-D optical path, there are three kinds of capability can be achieved, including the integration of high efficient laser and PD chips, the low-loss crystalline silicon waveguides, and the separated photonics-electronics design. From the measurement result, the transmission efficiency from input SMF to output MMF is -2.91 dB, and the propagation loss of silicon straight trapezoidal waveguides is as low as 0.404 dB/cm. A wide alignment tolerance of SMF-to-waveguide (> ±5 μm) and waveguide-to-MMF (> ±14 μm) is also achieved to facilitate the active device assembly. As compared to the conventional ridge waveguide using the dry-etching approach, the proposed 3-D optical path would be a cost-effective structure for the mass production.
In the second part of this dissertation, we proposed the 3-D power splitter for vertically-splitting waveguide and the vertical transition structure for active network optical path. Respect to the vertically-splitting waveguide, it is designed by the concept of using waveguide width difference between bus waveguide and branch waveguide. The monolithically embedded vertically-splitting structure with sidewall angle of 45˚ is used to vertically split the light and simultaneously connect the optics layer with the electronics layer of SOI substrate in the proposed chip-level optical interconnect systems. In this research, we experimentally demonstrated the 3-D 1×2 vertically-splitting waveguide with various power splitting ratios. The total transmission efficiency of proposed waveguide is around -6 dB, and the power splitting ratio of optical path 1 to optical path 2 can be controlled from 20%:80% to 46%:54% as the upper width of bus waveguide adjusts from 40 to 70 μm. The proposed vertically-splitting waveguide also provides the wider alignment tolerance (larger than ±13 µm at -1 dB power variation) for the active photonics device assembly.
The vertical-transition structures with 45˚ sidewall angle are first demonstrated in the SOI-based 3-D optical path. Such unique vertical-transition structures not only perform the vertical transition optical path but also provide a stage to integrate with the electrically controlled electro-absorption MQWs that is used to actively switch the optical path. Here, we experimentally demonstrated the 1×3 vertical-transition optical waveguide. Three clear light spots emitting from each output ports are observed by an IR camera. The total optical transmission efficiency can reach to -5.33 dB, and the corresponding optical transmission efficiency at output port 1, 2, and 3 are -10.81, -11.74, and -8.45 dB, respectively. A lower propagation loss of 0.178 dB/cm is also demonstrated by the cut-back method. Compared to the straight waveguide without any vertical-transition structures, the total splitter loss of 1×3 vertical-transition straight waveguide is 1.57 dB.
Finally, we first demonstrated the chip-level optical interconnect module combined with a VCSEL chip, a PD chip, a driver IC, and an amplifier IC on a SOI substrate. The unique point-to-point 3-D optical path is used to connect optical signal between transmitter and receiver. In this research, the VCSEL and PIN PD chips are flip-chip integrated on the electrical layer of SOI substrate to achieve complete chip-level optical interconnects. A higher VCSEL-to-PD optical coupling efficiency of -2.19 dB, a maximum optical power of 3.27 mW, and a low threshold current of 1 mA are achieved. The error-free data transmission of 10-Gbps can be also demonstrated when VCSEL is operated at the driving current of 9 mA. These measurement results verify that the proposed chip-level optical interconnect could be operated at a higher data rate and a lower power consumption using the proposed SOI-based 3-D optical paths.
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