| dc.description.abstract | In the process of manufacturing a chip, a circuit layout which is affected
by particles or design errors may cause that the chip operation differs with the
desired one. As a result, post-silicon debug becomes a critical and necessary
step in the current design flow. Therefore, instead of the iterative design
process, focused ion beam (FIB) technology is used to improve the time to
market by directly correcting the circuit layout.
As the manufacturing process evolves, the size of ICs is gradually reduced,
and the wire density of a circuit increases. However, FIB technology cannot
keep up with the evolution of the manufacturing process. Therefore, the FIB
cannot be easily used in probing or circuit editing, incurring the limitations of
testing and debugging. Since the influence of FIB is much larger than the line
spacing and width, the FIB process will affect several adjacent signal lines if
the wire density is too high. For example, only 30% signal lines for a circuit
using the 90-nm process can apply FIB.
The purpose of this thesis is to improve the FIB observable rate in the
detailed routing stage. We propose three FIB states (lookup, lookdown, and
lookpin) with their costs in the routing grid, and modify the wave propagation
stage in the maze routing to find a shortest path which has enough space to
process FIB for each net. Experimental results show that the proposed method
can achieve 100% routability with maximizing the number of signal lines which
can apply FIB.
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