| dc.description.abstract | In order to achieve high density, high bandwidth and high transmission, Through-Silicon-Via(TSV) has been widely used in three-dimensional chip integration thus resulting its density is increased. However the quality of signal transmission may be a tremendous problem on the ends of two signals interfering with each other. That is, we mentioned “coupling”.
This thesis is focused on the TSV coupling effect. Its main source is generated by the insulator capacitance between TSV and silicon substrate, and then coupling noise disperse from insulator to capacitance. The two most important coupling noises are “TSV-to-TSV coupling noise” and “TSV-to-circuit coupling noise”. And a signal transmission analysis platform for an advanced TSV model, called Vertical-Cross-Chain Substrate Structure (VCCSS), is performed to simulate and discuss with the TSV coupling effect, where the enhancement of the simulation accuracy is up to 11.5%. The TSV analysis platform, which can generate circuit architecture quickly and execute simulation analysis, is with the core by integrating the circuit simulation to Hspice or ADS. It is also to be extended to simulate the circuit with two kinds of substrate (EPI substrate & High-R substrate). If the analysis of the energy point of TSV is desired, this platform may automatically integrate the circuit simulation to ADS in order to reduce the time of setting up the circuit structure. Furthermore, we can achieve chip-stacking by using this analysis platform and then to analyze the whole circuit structure more carefully. Then we use a variety of shielding techniques, by changing the parameters of the process, the spacing between guard ring and TSV and different placement of guard ring in aggressor-victim pair array, we can observe the changes and suppression of vertical extension effect from bottom to top of TSV.
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