| dc.description.abstract | A typical stereo vision principle basically consists of two parts. One is the image extracted using two synchronous cameras, and another is a series of complex image processing. However, high-efficacy processors are often required to implement complex algorithms in software development. Thus, stereo vision is difficult to be achieved on the embedded system applications, because of its low-cost and limited resources. In this paper, we designed a high-efficiency segmentation hardware accelerator, based on SOM (Self-Organizing Map) neural network and using Hierarchical Robotic Discrete-Event Modeling, for color segmentation. Then, all the algorithms, connecting component labeling and stereo matching using SAD (Sum of Absolute Difference), were implemented as hardware and integrated with a pipeline controller. Finally, we synthesize a high-speed stereo vision as hardware system. As a result, our system is able to generate images at the speed of up to 13.8 images / sec. This performance makes our system usable in real-time embedded systems. Above all, we reduce the memory access times significantly and raise the performance effectively in high-efficiency segmentation hardware accelerator.
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