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姓名	林柏丞(Po-Chen Lin)  查詢紙本館藏	畢業系所	化學工程與材料工程學系
論文名稱	共濺鍍銅鈦薄膜之相分離演化機制與其對機械性質於3DIC接合的影響 (Effect of Phase Separation Evolution on Mechanical Strength of Co-sputtering Cu(Ti) Thin Film in 3DIC Bonding)
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摘要(中)	近年來，三維積體電路在半導體封裝製程中受到廣大的討論，除了有可能突破莫爾定律的限制，並且有著降低能源損耗，縮小元件體積，以及提高元件效能等優點。然而在尺寸越來越小的趨勢之下，封裝及接合的可靠度將越來越受重視。晶圓接合就成為3D-IC技術中的關鍵步驟。在眾多不同種的晶圓接合技術中，近年來以銅對銅熱壓接合技術為3D-IC的主流，不外乎是因為它的製程簡易以及成本較低的兩個原因。本研究中將使用簡易的共濺鍍技術將鈦加入銅中鍍製薄膜，研究其退火後反應以及應用於晶圓接合的影響。第一部分中，以討論單一銅鈦薄膜退火400 oC後之特性改變為主。藉由ESCA的縱深分布可發現含有不同鈦含量的銅鈦薄膜會有不同程度的相分離現象。由結果可得在四種不同鈦含量中，以15%鈦的相分離現象最為明顯，並且擁有150nm的銅層於表面。 相分離現象在眾多分析中皆可被證實，包括截面分析由高解析電子顯微鏡影像，以及其元素線掃描和面掃描可得，並且從場發電子維探儀中了解相分離後的表面形貌。實驗中，相分離後的試片其結晶特性與片電阻可由X-ray繞射分析及四點探針得知。本論文中所提相分離現象可由熱力學與動力學計算所證明。從動力學可得鈦擁有比銅大10倍的擴散速率，以及從熱力學來說，鈦有較傾向氧的能力相較於銅和矽。因此，本論文推斷鈦是主要的擴散因子，並且會朝向氧化矽基板方向擴散，同時銅會被推向往表面擴散，並且隨著時間增長形成一層無氧的純銅層。接著將鍍有銅鈦薄膜的基板採用面對面熱壓的方式接合，以觀察相分離對接合的影響。結果可得，利用含有15%鈦的銅鈦薄膜熱壓60分鐘可得到無孔洞的接合介面。接合介面的強度利用推力測試來檢測，其中發現接合時間越長以及相分離程度越明顯皆有助於接合強度的提升。 最後，本論文也提出相分離以及其接合的演化機制。並且可得知銅與鈦在共濺鍍銅鈦薄膜中相分離的結果提供了一個形成高品質銅接合的好方法。
摘要(英)	In recent years, three-dimension integration technology has been widely discussed in regard to the packaging industry. Because of its many advantages such as reductions in power and device size, an increase in efficiency, and the miniaturization of electronic devices, the reliability of bonding in packaging is becoming gradually more evident. Wafer-level bonding is a key aspect of three-dimension integrated circuits, and Cu-Cu thermocompression bonding has become main stream because of its low cost and simple processes. In this study, a simple co-sputter technology was used to add Ti into Cu to deposit Cu(Ti) films. First, the characteristics of a single Cu(Ti) film after annealing at 400 oC were investigated. We obtained samples with various Ti concentrations, and through in-depth profile analysis we determined that the samples exhibited different levels of phase separation. The results showed that the Cu(Ti) alloy films with 15% Ti contained approximately 150 nm of pure Cu near their sample surfaces. Evidence for phase separation was obtained from a cross section of high-resolution transmission electron microscopy images, line-scan images, and mapping images. Moreover, the morphology of the sample plane view was observed through electron probe microanalysis images and mapping. In the experiment, the crystal characteristics and sheet resistance were detected through grazing incidence X-ray diffraction and a four-point probe. Theoretically, the calculation of the diffusivity of Ti in Cu is one order of magnitude smaller than that of Cu in Cu. Both calculations prove thermodynamically and kinetically that Ti is a dominant diffusing species that is segregated near SiO2, whereas Cu atoms are pushed toward the surface. In this study, the films were bonded through thermocompression. A Cu(Ti) film containing 15 at% Ti with a bonding time of 60 min at 400 oC exhibited the highest bonding strength with no void caused by phase separation. The relationships between bonding strength and the samples with various Ti concentrations were measured over different bonding times through shear testing. Finally, the evolution of phase separation and bonding were proposed. From the results, we know that phase separation of Cu and Ti in co-sputtered Cu(Ti) films provides a innovative method for forming high-quality Cu bonds.
關鍵字(中)	★ 共濺鍍銅鈦 ★ 推力測試 ★ 銅銅接合 ★ 相分離	關鍵字(英)
論文目次	中文摘要 I Abstract II Acknowledgement IV Contents V List of Figures VII List of Tables X Ch.1 Introduction 1 1.1 Background 1 1.2 Direction of 3D-IC wafer-level bonding 5 1.2.1 Face-to-face method 5 1.2.2 Face-to-back method 5 1.3 Classification of 3D-IC wafer-level bonding 7 1.3.1 Fusion bonding 7 1.3.2 Anodic bonding 9 1.3.3 Adhesive bonding 11 1.3.4 Glass-frit bonding 11 1.3.5 Eutectic bonding 12 1.3.6 Metal thermal compression bonding 13 1.4 Cu-Cu wafer-level bonding in 3D-ICs 16 1.5 Co-sputter Cu(Ti) in bonding 22 1.6 The quality and reliability of bonding 23 Ch.2 Motivation 25 Ch.3 Experimental 28 Ch.4 Results and Discussion 32 4.1 Characteristics of single Cu(Ti) films 32 4.1.1 Electrical properties of Cu(Ti) films 32 4.1.2 Phase segregation of single Cu(Ti) film 34 4.1.3 Thermodynamic calculation 41 4.1.4 GIXRD results of Cu(Ti) film 46 4.1.5 HRTEM results of single Cu(Ti) film 49 4.1.6 Plane-view morphology of single Cu(Ti) film 55 4.2 Bonding quality of two face-to-face Cu(Ti) films 57 4.2.1 HRTEM results of bonding structure of Cu(Ti) 57 4.2.1 Shear test for bonding structure of Cu(Ti) 60 4.3 Mechanism of diffusion and phase separation 62 4.3.1 Mechanism for phase separation of a single Cu(Ti) film 62 4.3.2 Mechanism for face-to-face Cu(Ti) bonding 65 Ch.5 Conclusion 66 Reference 67
參考文獻	[1] K. Tu, "Recent advances on electromigration in very-large-scale-integration of interconnects," Journal of Applied Physics, vol. 94, pp. 5451-5473, 2003. [2] M.-Y. Guo, C. Lin, C. Chen, and K. Tu, "Asymmetrical growth of Cu 6 Sn 5 intermetallic compounds due to rapid thermomigration of Cu in molten SnAg solder joints," Intermetallics, vol. 29, pp. 155-158, 2012. [3] J. Ke, H. Chuang, W. Shih, and C. Kao, "Mechanism for serrated cathode dissolution in Cu/Sn/Cu interconnect under electron current stressing," Acta Materialia, vol. 60, pp. 2082-2090, 2012. [4] M.-H. Jeong, J.-W. Kim, B.-H. Kwak, and Y.-B. Park, "Effects of annealing and current stressing on the intermetallic compounds growth kinetics of Cu/thin Sn/Cu bump," Microelectronic Engineering, vol. 89, pp. 50-54, 2012. [5] M.-H. Jeong, G.-T. Lim, B.-J. Kim, K.-W. Lee, J.-D. Kim, Y.-C. Joo, et al., "Interfacial reaction effect on electrical reliability of Cu pillar/Sn bumps," Journal of Electronic Materials, vol. 39, pp. 2368-2374, 2010. [6] D. Sylvester and C. Wu, "Analytical modeling and characterization of deep-submicrometer interconnect," Proceedings of the IEEE, vol. 89, pp. 634-664, 2001. [7] A. Rahman and R. Reif, "System-level performance evaluation of three-dimensional integrated circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, pp. 671-678, 2000. [8] S. JOSE. (2001, November 28). International Technology Roadmap for Semiconductors Accellerates Pace to Smaller Chip Dimensions. [9] D. Amir and C. E. Bauer, "3D Packaging, Interconnection & Assembly," 2013. [10] J. U. Knickerbocker, "3D Integration & Packaging Challenges with through-silicon-vias (TSV)," 2012. [11] K. Sakuma, P. S. Andry, C. K. Tsang, S. L. Wright, B. Dang, C. S. Patel, et al., "3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections," IBM Journal of Research and Development, vol. 52, pp. 611-622, 2008. [12] H.-Y. You, Y.-S. Lee, S.-K. Lee, and J.-S. Kang, "Reliability of 20μm micro bump interconnects," in 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 2011, pp. 608-611. [13] A. Ostmann, A. Neumann, S. Weser, E. Jung, L. Bottcher, and H. Reichl, "Realization of a stackable package using chip in polymer technology," in Polymers and Adhesives in Microelectronics and Photonics, 2002. POLYTRONIC 2002. 2nd International IEEE Conference on, 2002, pp. 160-164. [14] H. Braunisch, S. N. Towle, R. D. Emery, C. Hu, and G. J. Vandentop, "Electrical performance of bumpless build-up layer packaging," in Electronic Components and Technology Conference, 2002. Proceedings. 52nd, 2002, pp. 353-358. [15] K.-S. Kao, S.-T. Wu, Y.-P. Hung, T.-C. Chang, R.-S. Cheng, and T.-H. Chen, "Application of numerical analysis to the reliability assessment of a novel package on package (PoP) structure for memory stacking," in Microsystems Packaging Assembly and Circuits Technology Conference (IMPACT), 2010 5th International, 2010, pp. 1-4. [16] K.-N. Chen, A. Fan, and R. Reif, "Microstructure examination of copper wafer bonding," Journal of Electronic Materials, vol. 30, pp. 331-335, 2001. [17] M.-F. Lai, S.-W. Li, J.-Y. Shih, and K.-N. Chen, "Wafer-level three-dimensional integrated circuits (3D-IC): Schemes and key technologies," Microelectronic Engineering, vol. 88, pp. 3282-3286, 11// 2011. [18] S. Farrens, S. Sood, and S. MicroTec, "Wafer-level packaging: Balancing device requirements and materials properties," in Proc. Pan Pacific Microelectron. Symp, 2014, pp. 22-24. [19] J. Lasky, "Wafer bonding for silicon?on?insulator technologies," Applied Physics Letters, vol. 48, pp. 78-80, 1986. [20] H. Ohashi, J. Ohura, T. Tsukakoshi, and M. Simbo, "Improved dielectrically isolated device integration by silicon-wafer direct bonding(SDB) technique," in 1986 International Electron Devices Meeting, 1986, pp. 210-213. [21] C. Rauer, F. Rieutord, J. Hartmann, A.-M. Charvet, F. Fournel, D. Mariolle, et al., "Hydrophobic direct bonding of silicon reconstructed surfaces," Microsystem Technologies, vol. 19, pp. 675-679, 2013. [22] Y. Backlund, K. Ljungberg, and A. Soderbarg, "A suggested mechanism for silicon direct bonding from studying hydrophilic and hydrophobic surfaces," Journal of Micromechanics and Microengineering, vol. 2, p. 158, 1992. [23] K. W. Yang, "The Study of Al-Ge Thin Films on Package," master, National Central University, 2009. [24] R. Joyce, K. Singh, H. Sharma, S. Varghese, and J. Akhtar, "Low cost anodic bonding for MEMS packaging applications," Microsystem Technologies, vol. 20, pp. 1153-1158, 2014. [25] S. Tatic-Lucic, J. Ames, B. Boardman, D. McIntyre, P. Jaramillo, L. Starr, et al., "Bond-quality characterization of silicon-glass anodic bonding," Sensors and Actuators A: Physical, vol. 60, pp. 223-227, 1997. [26] V. Kutchoukov, F. Laugere, W. van Der Vlist, L. Pakula, Y. Garini, and A. Bossche, "Fabrication of nanofluidic devices using glass-to-glass anodic bonding," Sensors and Actuators A: Physical, vol. 114, pp. 521-527, 2004. [27] C. R. Yang, "Research on Soeed and Quality of Anodic Bonding by Appling Arc Discharge," Chinese Society of Mechanical Engineers, 2006. [28] C.-T. Ko and K.-N. Chen, "Wafer-level bonding/stacking technology for 3D integration," Microelectronics Reliability, vol. 50, pp. 481-488, 4// 2010. [29] M. Abouie, Q. Liu, and D. G. Ivey, "Eutectic and solid-state wafer bonding of silicon with gold," Materials Science and Engineering: B, vol. 177, pp. 1748-1758, 2012. [30] R. Wolffenbuttel, "Low-temperature intermediate Au-Si wafer bonding; eutectic or silicide bond," Sensors and Actuators A: Physical, vol. 62, pp. 680-686, 1997. [31] Q. Liu, L. Du, Z. Zhao, L. Xiao, and X. Sun, "Localized Si–Au eutectic bonding around sunken pad for fabrication of a capacitive absolute pressure sensor," Sensors and Actuators A: Physical, vol. 201, pp. 241-245, 2013. [32] J. Fan, C. S. Tan, and Y. Pardhi, Low temperature wafer-level metal thermo-compression bonding technology for 3D integration: INTECH Open Access Publisher, 2012. [33] V. Dragoi, E. Cakmak, and E. Pabo, "Metal wafer bonding for MEMS devices," Romanian J. Inf. Sci. Technol, vol. 13, pp. 65-72, 2010. [34] B. Swinnen, W. Ruythooren, P. De Moor, L. Bogaerts, L. Carbonell, K. De Munck, et al., "3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias," in 2006 International Electron Devices Meeting, 2006, pp. 1-4. [35] Y.-S. Tang, Y.-J. Chang, and K.-N. Chen, "Wafer-level Cu–Cu bonding technology," Microelectronics Reliability, vol. 52, pp. 312-320, 2012. [36] K. Chen, C. Tan, A. Fan, and R. Reif, "Morphology and bond strength of copper wafer bonding," Electrochemical and Solid-State Letters, vol. 7, pp. G14-G16, 2004. [37] L. Peters, "Wafer-Level Packaging Slices MEMS Costs," Micromanufacturing, vol. 4, 2011. [38] S. J. Koester, A. M. Young, R. Yu, S. Purushothaman, K.-N. Chen, D. La Tulipe, et al., "Wafer-level 3D integration technology," IBM Journal of Research and Development, vol. 52, pp. 583-597, 2008. [39] K.-N. Chen and C. S. Tan, "Integration schemes and enabling technologies for three-dimensional integrated circuits," IET Computers & Digital Techniques, vol. 5, pp. 160-168, 2011. [40] G. Humpston and D. M. Jacobson, Principles of soldering: ASM international, 2004. [41] T.-H. Chuang, H.-J. Lin, and C.-W. Tsao, "Intermetallic compounds formed during diffusion soldering of Au/Cu/Al2O3 and Cu/Ti/Si with Sn/In interlayer," Journal of Electronic Materials, vol. 35, pp. 1566-1570, 2006. [42] C. C. Lee and S. Choe, "Fluxless In Sn bonding process at 140° C," Materials Science and Engineering: A, vol. 333, pp. 45-50, 2002. [43] R. W. Chuang and C. C. Lee, "High-temperature non-eutectic indium-tin joints fabricated by a fluxless process," Thin Solid Films, vol. 414, pp. 175-179, 2002. [44] C. Lee, W.-F. Huang, and J.-S. Shie, "Wafer bonding by low-temperature soldering," Sensors and Actuators A: Physical, vol. 85, pp. 330-334, 2000. [45] Y. Liling, L. Chengkuo, Y. Daquan, C. Won Kyoung, Y. Aibin, Y. Seung Uk, et al., "A hermetic chip to chip bonding at low temperature with Cu/In/Sn/Cu joint," in 2008 58th Electronic Components and Technology Conference, 2008, pp. 1844-1848. [46] M.-S. S. Chiou, T.-H. Lin, K.-H. Chen, C.-T. Chiu, H.-M. Tong, and K.-N. Chen, "Low temperature bonding of Sn/In-Cu interconnects for three-dimensional integration applications," 2013. [47] P. Gordon and T. Hurtony, "Investigation of the wetting properties of Cu 6 Sn 5 intermetallic compound," in 2015 38th International Spring Seminar on Electronics Technology (ISSE), 2015, pp. 315-319. [48] K. Bukat, J. Sitek, M. Koscielski, Z. Moser, W. Gasior, and J. Pstrus, "Investigation of the wetting of PCBs with SnCu (HASL) and Snimm finishes by SnZnBiIn solders," Soldering & Surface Mount Technology, vol. 24, pp. 4-11, 2012. [49] B.-J. Kim, G.-T. Lim, J. Kim, K. Lee, Y.-B. Park, H.-Y. Lee, et al., "Intermetallic compound growth and reliability of Cu pillar bumps under current stressing," Journal of Electronic Materials, vol. 39, pp. 2281-2285, 2010. [50] J. Cho, S. Yu, M. Roma, S. Maganty, S. Park, E. Bersch, et al., "Mechanism of low-temperature copper-to-copper direct bonding for 3D TSV package interconnection," in 2013 IEEE 63rd Electronic Components and Technology Conference, 2013, pp. 1133-1140. [51] S. E. Kim and S. Kim, "Wafer-level Cu–Cu direct bonding for 3D integration," Microelectronic Engineering, vol. 137, pp. 158-163, 2015. [52] C.-T. Ko and K.-N. Chen, "Low temperature bonding technology for 3D integration," Microelectronics Reliability, vol. 52, pp. 302-311, 2012. [53] Y. Hu, C. Liu, M. Lii, A. La Manna, K. Rebibis, M. Zhao, et al., "3D stacking using Cu-Cu direct bonding for 40um pitch and beyond," in Electronic System-Integration Technology Conference (ESTC), 2012 4th, 2012, pp. 1-5. [54] S. Koyama, N. Hagiwara, and I. Shohji, "Cu/Cu direct bonding by metal salt generation bonding technique with organic acid and persistence of reformed layer," Japanese Journal of Applied Physics, vol. 54, p. 030216, 2015. [55] C.-M. Liu, H.-w. Lin, Y.-C. Chu, C. Chen, D.-R. Lyu, K.-N. Chen, et al., "Low-temperature direct copper-to-copper bonding enabled by creep on highly (111)-oriented Cu surfaces," Scripta Materialia, vol. 78, pp. 65-68, 2014. [56] P. Gueguen, L. Di Cioccio, P. Gergaud, M. Rivoire, D. Scevola, M. Zussy, et al., "Copper direct-bonding characterization and its interests for 3D integration," Journal of The Electrochemical Society, vol. 156, pp. H772-H776, 2009. [57] T. Imamura, E. Higurashi, T. Suga, and R. Sawada, "Low-Temperature Direct Bonding of Flip-Chip Mountable VCSELs with Au-Au Surface Activation," IEEJ Transactions on Sensors and Micromachines, vol. 128, pp. 266-270, 2008. [58] E. Higurashi, T. Imamura, T. Suga, and R. Sawada, "Low-Temperature Bonding of Laser Diode Chips on Silicon Substrates Using Plasma Activation of Au Films," IEEE Photonics Technology Letters, vol. 19, pp. 1994-1996, 2007. [59] S. Tajima, S. Tsuchiya, M. Matsumori, S. Nakatsuka, and T. Ichiki, "High-rate reduction of copper oxide using atmospheric-pressure inductively coupled plasma microjets," Thin Solid Films, vol. 519, pp. 6773-6777, 8/1/ 2011. [60] R. Dohle, M. Petzold, R. Klengel, H. Schulze, and F. Rudolf, "Room temperature wedge–wedge ultrasonic bonding using aluminum coated copper wire," Microelectronics Reliability, vol. 51, pp. 97-106, 1// 2011. [61] A. Shigetou, T. Itoh, and T. Suga, "Direct bonding of CMP-Cu films by surface activated bonding (SAB) method," Journal of Materials Science, vol. 40, pp. 3149-3154, 2005. [62] F. Wang, L. Han, and J. Zhong, "Stress-induced atom diffusion at thermosonic flip chip bonding interface," Sensors and Actuators A: Physical, vol. 149, pp. 100-105, 1/15/ 2009. [63] W. Naoya and A. Tanemasa, "Behavior of Plated Microbumps during Ultrasonic Flip-Chip Bonding Determined from Dynamic Strain Measurement," Japanese Journal of Applied Physics, vol. 42, p. 2193, 2003. [64] T. Kazumasa, U. Mitsuo, T. Yoshihiro, T. Masamoto, K. Ryoichi, A. Yukiharu, et al., "Au Bump Interconnection with Ultrasonic Flip-Chip Bonding in 20 μm Pitch," Japanese Journal of Applied Physics, vol. 42, p. 2198, 2003. [65] J. Lee, J. H. Kim, and C. D. Yoo, "Thermosonic bonding of lead-free solder with metal bump for flip-chip bonding," Journal of Electronic Materials, vol. 34, pp. 96-102, 2005. [66] A. Shah, A. Rezvani, M. Mayer, Y. Zhou, J. Persic, and J. T. Moon, "Reduction of ultrasonic pad stress and aluminum splash in copper ball bonding," Microelectronics Reliability, vol. 51, pp. 67-74, 1// 2011. [67] H. Xu, V. L. Acoff, C. Liu, V. V. Silberschmidt, and Z. Chen, "Facilitating intermetallic formation in wire bonding by applying a pre-ultrasonic energy," Microelectronic Engineering, vol. 88, pp. 3155-3157, 10// 2011. [68] T. Takiya, N. Fukuda, I. Umezu, A. Sugimura, S. Ueguri, H. Yoshida, et al., "Low temperature bonding of metals by deposition of nanoparticles at the interface," Applied Physics Research, vol. 4, p. 42, 2012. [69] C. S. Tan and G. Y. Chong, "High throughput Cu-Cu bonding by non-thermo-compression method," in 2013 IEEE 63rd Electronic Components and Technology Conference, 2013, pp. 1158-1164. [70] P. Ding, W. Lanford, S. Hymes, and S. Murarka, "Effects of the addition of small amounts of Al to copper: Corrosion, resistivity, adhesion, morphology, and diffusion," Journal of Applied Physics, vol. 75, pp. 3627-3631, 1994. [71] J. D. McBrayer, R. Swanson, and T. Sigmon, "Diffusion of metals in silicon dioxide," Journal of The Electrochemical Society, vol. 133, pp. 1242-1246, 1986. [72] K. Hoshino, H. Yagi, and H. Tsuchikawa, "Effect of titanium addition to copper interconnect on electromigration open circuit failure," in Seventh International IEEE Conference on VLSI Multilevel Interconnection, 1990, pp. 357-359. [73] S. Tsukimoto, T. Morita, M. Moriyama, K. Ito, and M. Murakami, "Formation of Ti diffusion barrier layers in thin Cu (Ti) alloy films," Journal of Electronic Materials, vol. 34, pp. 592-599, 2005. [74] S.-Y. Hsu, H.-Y. Chen, and K.-N. Chen, "Cosputtered Cu/Ti bonded interconnects with a self-formed adhesion layer for three-dimensional integration applications," IEEE Electron Device Letters, vol. 33, pp. 1048-1050, 2012. [75] C. Liu and J.-S. Chen, "Low leakage current Cu (Ti)/SiO2 interconnection scheme with a self-formed TiOx diffusion barrier," Applied Physics Letters, vol. 80, pp. 2678-2680, 2002. [76] S. W. Russell, S. A. Rafalski, R. L. Spreitzer, J. Li, M. Moinpour, F. Moghadam, et al., "Enhanced adhesion of copper to dielectrics via titanium and chromium additions and sacrificial reactions," Thin Solid Films, vol. 262, pp. 154-167, 1995/06/15 1995. [77] D. Adams, T. L. Alford, S. A. Rafalski, M. J. Rack, S. W. Russell, M. J. Kim, et al., "Formation of passivation and adhesion layers for Cu via nitridation of Cu-Ti in an ammonia ambient," Materials Chemistry and Physics, vol. 43, pp. 145-152, 1996/02/01 1996. [78] D. Adams, T. L. Alford, N. D. Theodore, S. W. Russell, R. L. Spreitzera, and J. W. Mayer, "Passivation of Cu via refractory metal nitridation in an ammonia ambient," Thin Solid Films, vol. 262, pp. 199-208, 1995/06/15 1995. [79] C. J. Liu, J. S. Jeng, J. S. Chen, and Y. K. Lin, "Effects of Ti addition on the morphology, interfacial reaction, and diffusion of Cu on SiO2," Journal of Vacuum Science & Technology B, vol. 20, pp. 2361-2366, 2002. [80] M. J. Frederick, R. Goswami, and G. Ramanath, "Sequence of Mg segregation, grain growth, and interfacial MgO formation in Cu–Mg alloy films on SiO2 during vacuum annealing," Journal of Applied Physics, vol. 93, pp. 5966-5972, 2003. [81] M. J. Frederick and G. Ramanath, "Interfacial phase formation in Cu–Mg alloy films on SiO2," Journal of Applied Physics, vol. 95, pp. 3202-3205, 2004. [82] Y. S. Chien, Y. P. Huang, R. N. Tzeng, M. S. Shy, T. H. Lin, K. H. Chen, et al., "Low temperature (<180°C) wafer-level and chip-level In-to-Cu and Cu-to-Cu bonding for 3D integration," in 2013 IEEE 63rd Electronic Components and Technology Conference, 2013, pp. 1146-1152. [83] S. Koyama and I. Oya, "Effect of Formic Acid Surface Modification on Bond Strength of Solid-State Bonded Interface of Tin," Journal of the Japan Institute of Metals and Materials, vol. 73, pp. 809-815, 2009. [84] W. Yang, M. Akaike, M. Fujino, and T. Suga, "A Combined Process of Formic Acid Pretreatment for Low-Temperature Bonding of Copper Electrodes," ECS Journal of Solid State Science and Technology, vol. 2, pp. P271-P274, January 1, 2013 2013. [85] K. Woo, Y. Kim, B. Lee, J. Kim, and J. Moon, "Effect of Carboxylic Acid on Sintering of Inkjet-Printed Copper Nanoparticulate Films," ACS Applied Materials & Interfaces, vol. 3, pp. 2377-2382, 2011/07/27 2011. [86] K. Schroder, CRC handbook of electrical resistivities of binary metallic alloys: CRC Press, 1983. [87] D. R. Gaskell, Introduction to the Thermodynamics of Materials, Fifth Edition: CRC Press 2008. [88] A. Almazouzi, M. P. Macht, V. Naundorf, and G. Neumann, "Diffusion of manganese, chromium, and titanium in single crystalline copper," Physica Status Solidi (a), vol. 167, pp. 15-28, 1998. [89] K. Maier, C. Bassani, and W. Schule, "Self-diffusion in copper between 359 and 632 C," Physics Letters A, vol. 44, pp. 539-540, 1973. [90] C.-F. Tseng and J.-G. Duh, "Correlation between microstructure evolution and mechanical strength in the Sn–3.0 Ag–0.5 Cu/ENEPIG solder joint," Materials Science and Engineering: A, vol. 580, pp. 169-174, 2013. [91] K. N. Chen, S. M. Chang, L. C. Shen, and R. Reif, "Investigations of strength of copper-bonded wafers with several quantitative and qualitative tests," Journal of Electronic Materials, vol. 35, pp. 1082-1086, 2006.
指導教授	吳子嘉(Albert T. Wu)	審核日期	2017-1-11
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