博碩士論文 100521007 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:6 、訪客IP:3.85.143.239
姓名 黃昶暘( Chang-Yang Huang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用於生醫訊號具RC時間常數校正機制之低功率連續時間三角積分類比數位轉換器
(A Low-Power Continuous-Time Delta-Sigma ADC with RC Time-Constant Calibration Technique for Biomedical Signals Application)
相關論文
★ 應用於數位視頻廣播系統之頻率合成器及3.1Ghz寬頻壓控震盪器★ 地面數位電視廣播基頻接收器之載波同步設計
★ 適用於通訊系統之參數化數位訊號處理器核心★ 以正交分頻多工系統之同步的高效能內插法技術
★ 正交分頻多工通訊中之盲目頻域等化器★ 兆元位元率之平行化可適性決策回饋等化器設計與實作
★ 應用於數位視頻廣播系統中之自動增益放大器 及接受端濾波器設計★ OFDM Symbol Boundary Detection and Carrier Synchronization in DVB-T Baseband Receiver Design
★ 適用於億元位元率混合光纖與銅線之電信乙太接取網路技術系統之盲目等化器和時序同步電路設計★ 低複雜度與高速多速率多階有限脈衝響應數位濾波器設計技術
★ 以FPGA實現DVB-T/H系統之二維一維與AGC-CR通道等化技術★ 適用於IEEE 802.16系統並運用極座標架構之低複雜度MIMO STBC頻域等化器設計
★ HF頻帶無線供電植入式系統之高效率前端電路分析與設計★ 地面數位電視基頻接收器之同步電路設計
★ 應用於數位視頻廣播系統中具有自動增益控制之接受端濾波器設計★ 適用IEEE 802.16e標準之多碼率單埠記憶體LDPC解碼器設計
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 隨著醫學與超大型積體電路的快速成長,如今的生理訊號量測儀器已朝向可攜式發展,低功率的訴求在生醫應用中也日益重要。如何降低功耗與面積以滿足生醫儀器的可攜式和電池長效性已成為生醫應用的重要課題。
在生醫系統中,一個高解析度、低功耗的類比數位轉換器是重要的組成元件之一。藉由三角積分調變器 (DSM) 超取樣的特性,可有效降低前端類比濾波器設計的複雜度,進而減少整體晶片面積。然而一般的DSM大多是由交換式電容電路實現,為離散時間 (DT) 的系統。其開關快速切換的行為則需要更快的硬體來支援,這將造成大量的功率消耗,因此本論文選用連續時間 (CT) 的三角積分調變器以減緩硬體需求。此外,CT DSM本身具有反交疊濾波的特性,可進一步降低前端類比濾波器的複雜度。然而,CT DSM存在與溫度、製程變異嚴重相依的缺點,故本論文提出RC時間常數的校正方法,以自動補償RC時間常數的變異。此校正方法同時也能校正取樣頻率造成的係數偏差,因此即使取樣頻率發生變化,調變器中的迴路濾波器仍能正常運作。
本論文設計之CT DSM電路在10 kHz頻寬、128倍超取樣率、±0.5 V的輸入振幅以及1.8 V的供應電壓下,模擬可達到的訊號雜訊失真比 (SNDR) 為82.62 dB,有效位元 (ENOB) 為13.43位元,功率消耗約為76.98 μW (調變器+RC時間常數校正電路)。使用台積電TSMC 0.18μm CMOS 1P6M製程實現,其整體晶片面積約為1.408mX1.558m。
摘要(英) With the rapid development of the medical science and VLSI technology, the bio-signal measurement systems have been developed towards portability. Therefore, the low-power demands in biomedical application are increasingly important as well. How to reduce the power consumption and area for satisfying the portability as well as the long battery life-time requirements of biomedical instruments have become the important issues.
A high-resolution and low-power analog-to-digital converter is also one of the critical components that comprise the biomedical system. By taking the advantage of oversampling technique in delta-sigma modulators, the design complexity of analog anti-aliasing filter can be relaxed, and then resulting in reducing the overall chip area. However, the general DSMs consist of switched-capacitor (SC) circuit, so as a discrete-time system. The fast switching behavior of the switches requires a high-speed hardware to support, thus causing more power consumption. In this thesis, we choose the continuous-time delta-sigma modulators (CT-DSM) to ease the requirements of hardware. Furthermore, there is an inherent characteristic of implicit anti-aliasing filter in CT DSM; the design complexity of anti-aliasing filter can be further reduced as well. However, the drawback of a CT DSM is the dependence on the environment temperature and process variation. Therefore, the RC time-constant calibration method is proposed for automatically compensating the variations of RC time-constant. The method also can calibrate the coefficient errors introduced by the variation of sampling frequency. Even if the sampling frequency is changed, the function of loop filter in CT DSM still works very well.
The modulator achieves 82.62dB SNDR, 13.43bit ENOB, and power consumption 76.98μW at 10kHz signal bandwidth with X128 OSR, 1Vp-p amplitude, and 1.8V power supply. It’s fabricated in the TSMC 0.18μm 1P6M CMOS process, and chip area is 1.408mX1.558m.
關鍵字(中) ★ 連續時間
★ 離散時間
★ 三角積分調變器
★ 數位降頻濾波器
★ 反交疊濾波器
★ 雜訊轉移函數
★ 訊號轉移函數
★ 交換式電容電路
關鍵字(英) ★ Continuous-Time (CT)
★ Discrete-Time (DT)
★ Delta-Sigma Modulator (DSM)
★ Digital Decimation Filter
★ Anti-Aliasing Filter (AAF)
★ Noise Transfer Function (NTF)
★ Signal Transfer Function (STF)
★ Switched-Capacitor Circuit (SC)
★ Biquad Filter
論文目次 摘要 I
Abstract II
誌謝 III
目錄 IV
圖目錄 VII
表目錄 XII
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.2.1 典型的醫療儀器系統 2
1.2.2 應用三角積分調變器之醫療儀器系統 3
1.3 論文架構 4
第二章 連續時間三角積分類比數位轉換器介紹 5
2.1 連續時間三角積分A/D轉換器簡介 5
2.2 連續-離散時間之等效轉換 (CT-to-DT Conversion) 6
2.2.1 Impulse-Invariant Transform 7
2.2.2 Matched z-Transform 8
2.2.3 Backward Difference Transform 9
2.2.4 Forward Difference Transform 11
2.2.5 Bilinear Transform 12
2.2.6 總結 14
2.3 迴路濾波器函數分析 14
2.3.1 回授DAC之行為函數 15
2.3.2 雜訊轉移函數 (Noise-Transfer Function, NTF) 16
2.3.3 訊號轉移函數 (Signal-Transfer Function, STF) 22
2.4 降頻濾波器 (Decimation Filter) 23
第三章 非理想因素考量與系統模擬驗證 24
3.1 迴路延遲 (Excess-Loop Delay) 24
3.2 有限直流增益 (Finite DC-Gain) 27
3.3 有限單位增益頻寬 (Finite UGBW) 與迴轉率 (Slew-Rate) 30
3.4 時脈抖動 (Clock Jitter) 35
3.5 雜訊 (Noise) 43
3.6 製程變異 (Process Variation) 46
3.7 三角積分調變器系統模擬 54
第四章 連續時間三角積分調變器電路設計與模擬 57
4.1 系統電路 57
4.2 運算放大器 59
4.2.1 二級摺疊疊接組態放大器 (Two-Stage Folded-Cascode OPA) 59
4.2.2 共模回授電路 (Common-Mode Feedback, CMFB) 62
4.2.3 運算放大器電路設計 67
4.3 量化器與一位元NRZ數位類比轉換器 77
4.4 帶差參考電路 (Bandgap Reference Circuit) 78
4.5 RC時間常數校正電路 81
4.5.1 電壓-電流轉換電路 81
4.5.2 RC時間常數偵測電路 82
4.5.3 RC預測邏輯電路 (RC Prediction Logic) 83
4.6 DAC之參考電壓產生電路 84
4.7 數位降頻濾波器 (Decimation Filter) 85
4.8 系統模擬 86
第五章 晶片佈局與量測 89
5.1 晶片佈局 89
5.2 量測考量 91
5.2.1 輸入終端電路 (Input Terminal Circuit) 91
5.2.2 產生供應電壓 92
5.3 文獻比較 93
第六章 結論與未來展望 94
6.1 結論 94
6.2 未來展望 94
第七章 二階一位元量化之離散時間三角積分調變器 95
7.1 基本二階三角積分調變器 95
7.2 設計考量 96
7.2.1 交換式電容電路 (Switched-Capacitor Circuit) 96
7.2.2 運算放大器之有限直流增益 97
7.2.3 有限單位增益頻寬與迴轉率 99
7.2.4 雜訊分析 100
7.3 電路實現與模擬 101
7.4 量測考量與結果 103
7.5 文獻比較 104
參考文獻 106
參考文獻 [1]J. G. Webster, “Medical Instrumentation Application and Design,” Canada: John Wiley & Sons., 1998.
[2]K. Kiyoyama, Y. Tanaka, M. Onoda, “A Low Current Consumption Delta-Sigma Modulator for Body-Implanted Chip,” ISCAS 2006, May. 2006.
[3]C. H. Kuo, D. Y. Shi, K. S. Chang, “A Low-Voltage Fourth-Order Cascade Delta-Sigma Modulator in 0.18-μm CMOS,” IEEE Trans. Circuits and Syst., vol. 57, pp. 2450-2461, Sept. 2010.
[4]R. Schireir, G. C. Temes, “Understanding Delta-Sigma Data Converters,” John Wiley & Sons., Nov. 2004.
[5]R. C. Dorf, R. H. Bishop, “Modern Control Systems,” Eleventh Edition, Pearson Education, Aug. 2007.
[6]林弘益, “應用於生醫訊號之低功率數位降頻濾波器”, 國立中央大學電機工程學系碩士論文, 民國101年.
[7]M. Ortmanns, F. Gerfers, “Continuous-Time Sigma-Delta A/D Conversion – Fundamentals, Performance Limits and Robust Implementations,” Springer, Dec. 2005.
[8]R. Zanbaghi, P. K. Hanumolu, T. S. Fiez, “An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW,” IEEE Journal of Solid-State Circuits, vol. 48, no. 2, pp.487-501, Jan. 2013.
[9]J. A. Cherry, W. M. Snelgrove, “Clock Jitter and Quantizer Metastability in Continuous-Time Delta-Sigma Modulators,” IEEE Trans. Circuit Syst. II, vol. 46, no. 6, pp. 661-676, Jun. 1999.
[10]O. Oliaei, H. Aboushady, “Jitter Effects in Continuous Time ΣΔ Modulators with Delayed Return-to-Zero Feedback,” IEEE Int. Conf. Electron. Circuit Syst., vol 1, pp. 351-354, Sep. 1998.
[11]H. Tao, L. Toth, J. M. Khoury, “Analysis of Timing Jitter in Bandpass Sigma-Delta Modulators,” IEEE Trans. Circuits and Syst. II, vol. 46, no. 8, pp. 991-1001, Aug. 1999.
[12]S. Ali, S. Tanner, P. Farine, “Design and Analysis of a Power-Efficient Cascode- Compensated Amplifier,” ISOCC, pp. 96-99, Nov. 2012.
[13]H. Aminzadeh and R. Lotfi, “On The Power Efficiency Of Cascode Compensation Over Miller Compensation In Two-Stage Operational Amplifiers,” Journal of Circuits, Systems, and Computers, vol. 17, no. 1, 2008.
[14]H. Aminzadeh and R. Lotfi and S. Rahimian, “Design Guidelines for Two-Stage Cascode-Compensated Operational Amplifiers,” Proc. IEEE Int. Conf. on Electronics, Circuits and Systems, ICECS, pp. 264-267, 2006.
[15]L. Lah, J. Choma, J. Draper, “A Continuous-Time Common-Mode Feedback Circuit (CMFB) for High-Impedance Current-Mode Applications,” IEEE Trans. Circuits and Syst., vol. 47, no. 4, pp. 363-369, Apr. 2000.
[16]P. R. Gray, P. J. Hurst, S. H. Lewis, R. G. Meyer, “Analysis and Design of Analog Integrated Circuits,” Fifth Edition, John Wiley & Sons., Jan. 2009.
[17]B. Razavi, “Design of Analog CMOS Integrated Circuits,” Mcgraw-Hill, Second Edition, 2005.
[18]R. Castello, P. R. Gray, “A High-performance Micropower Switched-Capacitor Filter,” IEEE J. Solid-State Circuits, vol. SC-20, no.6, pp. 1122-1132, Dec. 1985.
[19]D. Senderowics, S. F. Dreyer, J. H. Huggins, C. F. Rahim, C. A. Laber, “A Faimly of Diff- erential CMOS Analog Circuits for a PCM Codec Filter Chip,” IEEE J. Solid-State Circuits, vol. SC-17, pp.1014-1023, Dec 1981.
[20]R. V. Prathamesh, “Mapping Controllers from the S-Domain to the Z-domain Using Mag- nitude Invariance and Phase Invariance Methods,” Bachelors of Electronics Engineering, Pune University, 2004.
[21]R. Joacob Baker, “CMOS Mixed-Signal Circuit Design,” Wiley-IEEE Press, Second Edition, 2009.
[22]X. Bo, Y. Shouli, E. Sanchez-Sinencio, “An RC Time Constant Auto-Tuning Structure for High Linearity Continuous-Time ΣΔ Modulator and Active Filter,” IEEE Trans. Circuits and Syst. I, vol. 51, no. 11, pp, 2179-2188, Nov. 2004.
[23]林妤穎, “兼併切換式電容及切換式放大器且應用於生醫訊號之三角積分調變器,” 國立中央大學電機工程學系碩士論文, 民國九十九年.
[24]J. Sauerbrey, T. Tille, D. Schmitt-Landsiedel, R. Thewes, “A 0.7-V MOSFET-Only Switched- Opamp Σ Δ Modulator in Standard Digital CMOS Technology”, IEEE J. Solid-State Circuits, vol. 37, no.12, Dec. 2002.
[25]H.-Y. Lee, C.-M. Hsu, S.-C. Huang, Y.-W. Shih, and C.-H. Luo, “Designing Low Power of Sigma Delta Modulator for Biomedical Application,” Biomed. Eng. Applicat., Basis, Commun., no. 18, pp. 181–185, August 2005.
[26]H. Y. Yang and R. Sarpeshkar, “A Bio-Inspired Ultra-Energy-Ef?cient Analog-to-Digital Converter for Biomedical Applications,” IEEE Trans. Circuits Syst. I, vol. 53, no. 11, ]pp. 2349–2356, Nov. 2006.
[27]S. Y. Lee and C. J. Cheng, “A Low-Voltage and Low-Power Adaptive Switched-Current Sigma–Delta ADC for Bio-Acquisition Microsystems,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 12, pp.2628–2636, Dec. 2006.
[28]C.-M. Hsu, T.-C. Yo, C.-H. Luo, “An Ultra-Low Power Variable-Resolution Sigma-Delta Modulator for Signals Acquisition of Biomedical Instrument,” IEICE trans. Electron., Vol. E90-C,No.9, December 2007.
[29]H.-L. Chen, P.-S. Chen, J.-S. Chiang, “A Low-Offset Low-Noise Sigma- Delta Modulator with Pseudorandom Chopper-Stabilization Technique,” IEEE Trans. Circuits Syst. I, vol. 56, no. 12, December 2009.
[30]E. Lopez-Morillo, R. G. Carvajal, F. Munoz, H. El Gmili, A. Lopez-Martin, J. Ramirez- Angulo, “A 1.2-V 140-nW 10-bit Sigma–Delta Modulator for Electroencephalogram Applications,” IEEE Trans. Biomed. Circuits and Syst., vol. 2, no.3, Sept. 2008.
[31]F. Gerfers, M. Ortmanns, Y. Manoli, “A 1.5-V 12-bit Power-Efficient Continuous- Time Third-Order ΣΔ Modulator,” IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1343-1352, Aug. 2003.
[32]M. Keller, A. Buhmann, J. Sauerbrey, M. Ortmanns, Y. manoli, “A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma-Delta Modulators,” IEEE Trans. Circuits Syst. I, vol. 55, no. 11, pp. 3480- 3487, Dec. 2008.
[33]M. Ortmanns, F. Gerfers, Y. Manoli, “A Continuous-Time Sigma-Delta Modulator with Switched Capacitor Controlled Current Mode Feedback,” Proc. Eur. Solid- State Circuits Conf., pp. 249-252, Sept. 2003.
[34]Y. Shouli, E. Sanchez-Sinencio, “A Continuous-Time ΣΔ Modulator with 88-dB Dynamic Range and 1.1-MHz Signal Bandwidth,” IEEE. J. Solid-State Circuits, vol. 39, no. 1, pp. 75-86, Jan. 2004.
[35]M. Ortmanns, F. Gerfers, Y. Manoli, “A Continuous-Time ΣΔ Modulator with Reduced Sensitivity to Clock Jitter Through SCR Feedback,” IEEE Trans. Circuits Syst. I, vol. 52, no. 5, pp. 875-884, May 2005.
[36]R. Schoofs, M.S.J. Steyaert, W. Sansen, “A Design-Optimized Continuous-Time Delta-Sigma ADC for WLAN Applications,” IEEE Trans. Circuits Syst. I, vol. 54, no. 1, pp. 209-217, Jan. 2007.
[37]K. Matsukawa, Y. Mitani, M. Takayama, K. Obata, S. Dosho, A. Matsuzawa, “A Fifth-Order Continuous-Time Delta-Sigma Modulator with Single-Opamp Res -onator,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 697-706, April 2010.
[38]S. Pavan, N. Krishnapura, R. Pandarinathan, P. Sankar, “A Power Optimized Continuous-Time ΔΣ ADC for Audio Applications,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 351-360, Feb. 2008.
[39]F. Gerfers, M. Ortmanns, Y. Manoli, “A 12-Bit Power Efficient Continuous-Time ΣΔ Modulator with 250 μW Power Consumption,” Proc. Eur. Solid-State Circuits Conf., pp. 538-541, Sept. 2001.
[40]M. Ortmanns, F. Gerfers, Y. Manoli, “Compensation of Finite Gain-Bandwidth Induced Errors in Continuous-Time Sigma-Delta Modulators,” IEEE Trans. Circuits Syst. I, vol. 51, no. 6, pp. 1088-1099, June 2004.
[41]F. Gerfers, M. Ortmanns, L. Samid, Y. Manoli, “Implementation of a 1.5V Low- Power Clock-Jitter Insensitive Continuous-Time ΣΔ Modulator,” IEEE. Intel. Symp. Circuits and Syst., vol. 2, pp. II-652-II-655, May 2002.
[42]F. Colodro, A. Torralba, “New Continuous-Time Multibit Sigma-Delta Modulators with Low Sensitivity to Clock Jitter,” IEEE Trans. Circuits Syst. I, vol. 56, no. 1, pp. 74-83, Jan. 2009.
[43]K. Chien-Hung, S. Deng-Yao, C. Kang-Shuo, “A Low-Voltage Fourth-Order Cascade Delta-Sigma Modulator in 0.18-μm CMOS,” IEEE Trans. Circuits Syst. I, vol. 57, no. 9, pp. 2450-2461, Sept. 2010.
[44]K. Chien-Hung, L. Kuan-Yi, C. Shuo-Chau, “A 0.8V SOP-Based Cascade Multibit Delta-Sigma Modulator for Wideband Applications,” IEEE Asia Pacific Conf. Circuits Syst., pp. 1224-1227, Dec. 2008.
[45]李冠毅, “使用AB類/AB類開關運算放大器技術之0.7伏低功率低失真多位元三角積分調變器,” 國立臺灣師範大學應用電子科技學系碩士論文, 民國九十九年一月.
[46]郭建宏, “低電壓CMOS三角積分調變器的設計與實現,” 國立臺灣大學博士論文, 民國九十二年六月.
[47]L. Chi Fung, “Multimode Switched-Capacitor Delta-Sigma Analog-to-Digital Con- verter,” Degree of Master of Philosophy in Department of Electronic and Com- puter Engineering, Hong Kong University of Science and Technology, Aug. 2007.
[48]Omid Shoaei, “Continuous-Time Delta-Sigma A/D Converters for High Speed Applications,” Degree of Doctor of Philosophy, Faculty of Graduate Studies and Research in Partial Fulfilment of the Requirements, Carleton University, 1995.
指導教授 薛木添(Muh-Tian Shiue) 審核日期 2014-1-20
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明