| 摘要(英) |
In today’s nanometer IC process, process variation in devices is a common phenomenon. This process variation problem gets exponentially worse as device size shrinks, which will become a big issue in the future.
If process variation changes the chip performance too much, it could make the design fail to meet the specification and reduce the design yield. Before tape-out, foundry will ask the customer to do corner analysis as least to guarantee the design yield.
The goal of corner analysis is to find the worst-case performance values across all PVT corners. If the yield is not good, the designers can redesign the circuits before tape out. Traditionally, there are only 5 process corners. It’s quite easy to run full corner analysis. In modern designs, the variations of supply voltage and temperature should be considered, too. Therefore, there can be hundreds or thousands of PVT corners. This is quite time-consuming to run full corner analysis.
This thesis proposes an algorithm to extract the most relevant corners to be simulated. Instead of full corner analysis, only a few simulations are enough to find the worst case among all corners. As shown in the experimental results, this approach greatly improves the efficiency and accuracy of design yield analysis. |
| 參考文獻 |
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[12] Solido Design Automation Inc, “Variation-Aware Custom IC Design: Improving PVT and Statistical Maximum Yield at the Performance Edge ”
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[15] Solido Design Automation Inc, “High-Sigma Monte Carlo for High Yield and Performance Memory Design” |
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