具高速相位選擇器之六十億赫茲全數位式展頻時脈產生器

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姓名

黃映祥(Ying-Hsiang Huang) 查詢紙本館藏

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電機工程學系

論文名稱

具高速相位選擇器之六十億赫茲全數位式展頻時脈產生器
(A 6 GHz All-digital Spread-spectrum Clock Generator with High Speed Phase Selector)

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摘要(中)

摘要
本論文提出一個操作在6 GHz、擁有10個相位輸出全數位式展頻時脈產生器。在此設計中，本設計使用含有次回授迴圈之多重相位數位控制震盪器，因此可在相位多的情況下仍能有高頻率輸出。提出一個高速相位選擇器可以在6 GHz操作速度下做多相位的切換，相位選擇器中的相位選擇單元可以限制各節點所看到的負載，因此操作速度不受相位個數所影響。使用混亂波做為展頻機制的調變波型，藉以達到比其他種調變波型更多的電磁雜訊干擾衰減量。
本論文之全數位式展頻時脈產生器使用TSMC 90 nm MSG 1P9M CMOS製程實現晶片，其操作頻率為6 GHz，並且擁有10個相位的輸出。電路在操作電壓為1 V時，功率消耗為46 mW，而使用三角波調變的展頻機制對於電磁雜訊的衰減量為15.83 dB，使用混亂波調變的展頻機制對於電磁雜訊的衰減量為18.64 dB。整體晶片面積為830 × 830 um2，核心電路的面積為130 × 234 um2。

摘要(英)

Abstract
A 6 GHz all-digital spread-spectrum clock generator with 10-phase output has been presented in this thesis. A multi-phase digitally-controlled oscillator with sub-feedback loop has been used in this design, as a result, this circuit can be operating at high frequency with many outputs. The proposed high speed phase selector can switch phase at 6 GHz operating frequency. The phase-selecting unit in the phase selector makes load of each nodes limited, therefore, the operating frequency isn’t affected by the amount of phase. The chaotic modu- lation used in the spread-spectrum mechanism increases the more reduction of electromagne- tic interference with comparison to other modulations.
The proposed all-digital spread-spectrum clock generator has been fabricated in TSMC 90 nm MSG 1P9M CMOS process with 10-phase output at 6 GHz operating frequency. The power consumption is 46 mW under 1 V supply voltage. The reduction of electromagnetic interference are 15.83 dB with the spread-spectrum mechanism modulated by triangular wave and 18.64 dB with the spread-spectrum mechanism modulated by chaotic wave. The chip area is 830 × 830 um2. The core area is 130 × 234 um2.

關鍵字(中)

★ 全數位式
★ 全數位式展頻時脈產生器
★ 混亂波調變
★ 全數位式鎖相迴路
★ 高速相位選擇器

關鍵字(英)

★ All-digital
★ All-digital Spread-spectrum Clock Generator
★ Chaotic Wave
★ All-digital Phase-locked Loop
★ High Speed Clock Generator
★ ADSSCG

論文目次

目錄
摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 vii
表目錄 x
第1章緒論 1
1.1 研究動機 1
1.2 研究目的及其應用 2
1.3 論文架構 2
第2章全數位式展頻時脈產生器先前技術探討 3
2.1 鎖相迴路簡介 3
2.2 展頻時脈產生器簡介 4
2.3 先前技術探討 7
2.3.1 輸入參考時脈調變技術 7
2.3.2 直接控制數位控制震盪器之數位碼調變技術 8
2.3.3 控制多模數除頻器除率之調變技術 9
2.3.4 選擇多相位輸出之調變技術 10
2.4 預計論文規格 11
第3章利用多相位數位控制震盪器做相位選擇式的全數位式展頻時脈產生器 13
3.1 設計概念 13
3.2 多相位數位控制震盪器 14
3.2.1 多相位數位控制震盪器公式探討[15] 14
3.2.2 多相位數位控制震盪器架構 16
3.2.3 多相位數位控制震盪器內部電路 17
3.2.4 多相位數位控制震盪器佈局考量 19
3.2.5 多相位數位控制震盪器模擬結果 20
3.3 雙路徑相位選擇器 21
3.3.1 雙路徑相位選擇器之電路架構 21
3.3.2 雙路徑相位選擇器內部電路 23
3.3.3 雙路徑相位選擇器佈局考量 25
3.3.4 雙路徑相位選擇器模擬結果 26
第4章操作在6 GHz之全數位式展頻時脈產生器 29
4.1 電路架構與操作 29
4.1.1 全數位式鎖相迴路之操作 30
4.1.2 全數位式展頻時脈產生器之操作 31
4.2 鎖相迴路系統分析[16] 32
4.2.1 全數位式鎖相迴路之S-domain分析 32
4.2.2 電荷幫浦鎖相迴路之S-domain分析 33
4.2.3 計算數位迴路濾波器之參數 34
4.3 全數位式鎖相迴路之子電路設計 36
4.3.1 相位頻率偵測器 36
4.3.2 時間對數位轉換器 37
4.3.3 數位迴路濾波器 41
4.4 全數位式展頻時脈產生器之子電路設計 42
4.4.1 隨機數字產生器 42
4.4.2 隨機數字對數位碼解碼器 43
4.4.3 差異積分調變器 46
4.4.4 選擇碼產生器 47
第5章電路模擬與晶片量測結果 49
5.1 設計流程 49
5.2 佈局前電路模擬 49
5.2.1 全數位式鎖相迴路 49
5.2.2 全數位式展頻時脈產生器 50
5.3 電路佈局與佈局後電路模擬 52
5.4 晶片照相與量測環境設定 56
5.5 量測結果 61
5.6 規格比較 66
第6章結論與未來研究方向 69
6.1 結論 69
6.2 未來研究方向 69
參考文獻 71

參考文獻

參考文獻
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指導教授

鄭國興

審核日期

2013-11-29

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