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姓名 許庭嘉(Ting-chia Hsu) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 一體成型鍺量子點/二氧化矽/矽異質結構之形成與其介面工程探討
(Formation of self-organized Ge quantum dots/SiO2/silicon heterostructures with interface engineering)相關論文 檔案 [Endnote RIS 格式]
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摘要(中) 本論文利用選擇性氧化複晶矽鍺奈米柱/氮化矽/矽基材結構來成長製作一體成型之鍺量子點/二氧化矽/矽的金氧半異質結構。此量子點的形成是利用矽鍺氧化優先將矽氧化生成二氧化矽且析出鍺再匯聚而成。所形成的鍺量子點進一步催化鄰近氮化矽的局部氧化，進而鑽入並穿透氮化矽碰觸到矽基板。在此同時，鍺量子點的外圍披覆有一層4 nm厚的二氧化矽，並有一約3-5 nm之矽鍺層穿透此二氧化矽滲入下方矽基板之表面，形成一體成型之鍺量子點/二氧化矽/矽的金氧半異質結構。由於此二氧化矽是由矽在高溫下熱氧化所生成，因此有很好的矽鍺/二氧化矽介面特性，可作為矽鍺的閘介電層。而且此薄薄的二氧化矽可以有效地舒緩鍺量子點與矽之間的晶格失配，形成品質良好的鍺/二氧化矽/矽金氧半異質接面。
透過變溫高低頻之電容-電壓量測分析，吾人可萃取出鍺量子點與二氧化矽之介面缺陷密度約2×1011 cm-2eV-1 ，足以佐證本文所提出之鍺/二氧化矽/矽的介面具有元件等級的介面品質。另外，對直徑大小約75-90 nm的鍺量子點進行拉曼量測分析，可清楚觀察到較小的鍺量子點感受到周圍介質所施予更大的壓縮應力。進一步計算分析可知，當鍺量子點鑽入矽基板內的體積比例愈大，受到氮化矽與矽介層的壓縮應力影響愈高，與實驗觀察結果相符。由此可知，本文所提出之一體成型之鍺量子點/二氧化矽/矽的金氧半異質結構不僅可以同時得到Ge/Si與Ge/SiO2良好的介面，更可以透過調變鍺量子點的大小尺寸與鑽入矽基板的深度來進行鍺量子點的介面應力工程化，非常有利於日後鍺金氧半電晶體之製作。摘要(英) In this thesis, we demonstrated a novel method for the fabrication of a designer Ge quantum dot (QD)/SiO2/Si heterostructure by selectively oxidizing poly-Si0.83Ge0.17 nano-pillars over buffer layers of Si3N4 that were deposited over Si substrates. The formation of Ge QDs was realized by thermally oxidizing the SiGe pillar through the preferential oxidation of Si, the segregation of released Ge to be incorporated within the as-yet unoxidized SiGe grains, and ultimately the Ostwald ripening of the Ge QD. Attendant to the formation of Ge QDs, catalytically-enhanced local oxidation of Si3N4 by Ge QD itself also facilitates the QD penetration through Si3N4, ultimately leading to the QDs in contact with the underlying Si substrate. An approximately 4-nm-thick interfacial layer of oxide was observed at the interface of Ge QD/Si substrate in conjunction with the presence of a 3-5 nm SiGe intermixing shell at the interface of Si substrate, generating a self-organized Ge QD/SiO2/Si heterostructure. Thereby we are able to not only create an entirely new heterostructure interface with the Si substrate, but also grow superior SiO2 directly over Ge.
Ge QD experiences compressive strain from the Si substrate, and Raman characterization reveals that the compressive stress is much enhanced with a reduction in the QD size. The interfacial quality of the Ge QD/SiO2/Si heterstructure is further characterized on a metal-oxide-semiconductor (MOS) diode. The extracted interface trap density (Dit) from temperature-dependent high- and low-frequency capacitance-voltage (C-V) characteristics was about 2×1011 cm-2eV-1, indicating the high quality of the SiO2/Ge QD interface being favorable for the realization of Ge MOS devices with good oxide integrity.關鍵字(中) ★ 鍺量子點
★ 異質結構
★ 介面工程關鍵字(英) 論文目次 目錄
中文摘要 i
英文摘要 iii
致 謝 v
目 錄 vii
圖目錄 ix
表目錄 xiii
第一章 簡介 1
1-1 前言 1
1-2 鍺通道應用於電晶體之可能電荷傳輸特性的回顧與分析 2
1-3 鍺基板介面工程 3
1-4 研究動機 5
1-5 論文的整體架構 5
第二章 鍺量子點與矽基板的異質結構設計 11
2-1 前言 11
2-2 平面矽鍺氧化形成鍺量子點與鍺量子點在氮化矽中的移動 11
2-3 利用矽鍺柱氧化形成鍺量子點作為電晶體通道 13
2-3-1 矽鍺柱氧化生成二氧化矽的膨脹比例 14
2-3-2 矽鍺柱氧化形成鍺量子點通道的尺寸掌控 15
2-3-3 矽/鍺異質接面 16
2-3-4 鍺量子點與氧化生成的二氧化矽介面 17
2-4 鍺量子點電容結構設計 18
第三章 鍺量子點的結晶性與應力工程探討 34
3-1 前言 34
3-2 鍺量子點的結晶性與晶格方向 34
3-3 鍺量子點與周圍環境的應力討論 36
3-4 鍺量子點與鑽入矽基板的體積及表面積與所受應力之關係探討 38
第四章 鍺量子點電容元件製作流程與量測分析 44
4-1 前言 44
4-2 鍺量子點電容製程條件設計 44
4-3 鍺量子點電容製作流程 46
4-4 鍺量子點電容特性量測分析與介面缺陷密度計算 48
第五章 總結與未來展望 59
參考文獻 60參考文獻 [1] T. Ghani et al., “A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors,” IEDM Tech. Dig., p. 11.6.1, 2003.
[2] D. Kuzum, “Interface-engineered Ge MOSFETs for future high performance CMOS applications,” dissertation for the degree of doctor, Stanford university, 2009.
[3] S. Takagi, “Re-examination of subband structure engineering in ultra-short channel MOSFETs under ballistic carrier transport,” VLSI Symp. Dig., p. 115, 2003.
[4] Y. Yang et al., “Electron mobility enhancement in strained-germanium n-channel metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 91, p. 102103, 2007.
[5] T. Krishnamohan et al., “High mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: Experiments,” IEEE Trans. Elec. Dev., vol. 53, p. 990, 2006.
[6] T. Krishnamohan et al., “Comparison of (001), (110) and (111) Uniaxial- and Biaxial- Strained-Ge and Strained-Si PMOS DGFETs for All Channel orientations: Mobility Enhancement, Drive Current, Delay and Off-State Leakage,” IEDM Tech. Dig., p. 1, 2008.
[7] D. Kuzum et al., “Interface-Engineered Ge (100) and (111), N- and P-FETs with High Mobility,” IEDM Tech. Dig., p. 723, 2007.
[8] C. Chui et al., “Nanoscale germanium MOS dielectrics- Part I: Germanium oxynitrides,” IEEE Trans. Elec. Dev., vol. 53, p. 1501, 2006.
[9] K. Martens et al., “On the correct extraction of interface trap density of MOS devices with high-mobility semiconductor substrates,” IEEE Trans. Elec. Dev., vol. 55, p. 547, 2008.
[10] M. Frank et al., “Hafnium oxide gate dielectrics on sulfur-passivated germanium,” Appl. Phys. Lett., vol. 89, p. 112905, 2006.
[11] D. Kuzum et al., “Ge Interface Engineering with Ozone Oxidation for Low Interface State Density,” IEEE Elec. Dev. Lett., vol. 29, p. 328, 2008.
[12] P. W. Li et al., “Formation of atomic-scale Germanium quantum dots by selective oxidation of SiGe/Si-on-Insulator,” Appl. Phys. Lett., vol. 83, p. 4628, 2003.
[13] W. T. Lai and P. W. Li, “Growth kinetics and related physical/electrical properties of Ge quantum-dots formed by thermal oxidation of Si1-xGex-on-insulator,” Nanotechnology, vol. 18, p. 145402, 2007.
[14] K. H. Chen et al., “Precise Ge quantum dot placement for quantum tunneling devices,” Nanotechnology, vol. 21, p. 055302, 2010.
[15] J. E. Chang et al., “Matrix and quantum confinement effects on optical and thermal properties of Ge quantum dots,” Journal of Physics D: Applied Physics, vol. 45, p. 15303, 2012.
[16] C. Y. Chien et al., “Nanoscale, catalytically enhanced local oxidation of silicon-containing layers by ‘burrowing’ Ge quantum dots,” Nanotechnology, vol. 22, p. 435602, 2011.
[17] 張宇瑞，“鍺量子點在氮化矽中的形成機制與鍺量子點可見光光二極體的研製”，碩士論文，國立中央大學，民國一百年。
[18] C. Y. Chien et al., “Formation of Ge quantum dots array in layer-cake technique for advanced photovolatics,” Nanotechnology, vol. 21, p. 505201, 2010.
[19] C. C. Wang et al., “CMOS-compatible generation of self-organized 3D Ge quantum dot array for photonic and thermoelectric applications,” IEEE Trans. Nanotechnology, vol. 11, p. 657, 2012.
[20] M. H. Kuo et al., “Designer Ge quantum dots on Si: A heterostructure configuration with enhanced optoelectronic performance,” Appl. Phys. Lett., vol. 101, p. 223107, 2012.指導教授 李佩雯(Pei-wen Li) 審核日期 2013-8-20 推文 plurk
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