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姓名 林庚諭(Keng-Yu Lin) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 微型矽鍺奈米柱熱電致冷器製備與研究
(Experimental demonstration of SiGe Nanopillars)相關論文 檔案 [Endnote RIS 格式]
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摘要(中) 隨著電子元件操作功率、運算速度和積體電路密度不斷提升，元件操作時所帶來的高溫將反噬電子元件的操作效能，且元件損壞之機率將以指數方式增加。由於一般積體電路運作時並非整體皆會產生高熱，通常只有局部電路會有過熱的現象，亦即一般所謂的熱點（Hot spot）。以現今之半導體產業來說，如果要將熱電致冷器整合於積體電路中以達到熱管理之功用，唯有使用矽基材料才可相容。本實驗室先前已完成矽鍺柱薄膜熱導率與電導率相關研究，其中矽鍺合金24%之奈米柱薄膜經由估算，其400K 時的ZT達約0.31。因此，本研究使用矽鍺合金奈米柱陣列作為熱電致冷元件之核心材料。
將矽鍺薄膜透過微影佐以蝕刻製程製作出邊長尺寸均為300 nm 且高度達1 μm之矽鍺柱陣列，再分別重摻雜為N 型（1×1020 cm-3）與P 型（2×1019 cm-3）。巧妙地藉由金屬矽化製程與掀離製程（lift-off）將金屬NiSi 作為N 型與P 型矽鍺柱之間的連結，成功地完成矽鍺熱電致冷元件。本研究所製作矽鍺陣列尺寸分別為18×25 μm2與36×28 μm2的元件中。尺寸為18×25 μm2 之熱電致冷元件在環境溫度30℃時，僅需供給28 mA 即能達到3.7℃之致冷峰值；尺寸為36×28 μm2 於環境溫度60 oC 之致冷溫度曲線，於通入電流68 mA 時，最高致冷溫度峰值為4.5℃。總觀上述實驗結果，透過高摻雜濃度、結構尺寸、材料之間介陎所增強的邊界散射、合金散射以及聲子-聲子散射機制有效地保持電傳導率，降低熱導率，進而提升矽鍺奈米柱陣列之熱電轉換效率，使通以小電流的矽鍺熱電致冷元件在30℃和60℃的環境溫度時就有相當程度的冷卻溫度。摘要(英) With the rapid miniaturization of electric devices to boost the switching speed and to increase the number of components per integrated circuit (IC) chip, performance and
reliability of devices are severely threatened by localized hot spots where the temperature is much higher than the surrounding environmental regions. Si-based thermoelectric (TE) microcooler has being expected to offer an efficient method for thermal management of Si IC, since it can provide in situ local cooling for specific hot spots. Si-Ge materials are highly scalable and appropriate for chip-level cooling due to the ease of integration with the prevailing CMOS ICs and more importantly, a reasonable TE figure of merit, ZT. In thisthesis, we demonstrated a novel fabrication of Si0.76Ge0.24 nanopillar TE cooler.
Combinational electronic-beam lithography and plasma etching technologies were performed to produce 300-nm-diameter, 1000-nm-height poly-SiGe pillars, followed by ion
implantation of either boron or phosphorus. The doping concentrations are 1×1020 cm-3(P) and 2×1019 cm-3(B) for n-type and p-type nanopillars. Metal interconnects between n- and p-type nanopillars were realized by the Ni silicidation and the Al contact electrodes were formed using lift-off processes. The cooling temperature was measured using the four-point-probe technique at 303K and 333K, respectively. The maximum cooling temperatures of 3.7K(measured at 303K) and 4.5K(measured at 333K) were measured on the SiGe pillar
cooler of 36×28 μm2. The reasonable good cooling performance of SiGe TE microcooler possibly results from the good electrical conductivity of heavily doped p-n SiGe pillar array and the significantly reduced thermal conductivity of SiGe nanopillar as a consequence of alloy, boundary and phonon-phonon scattering.關鍵字(中) ★ 熱電致冷器
★ 矽鍺合金關鍵字(英) 論文目次 中文摘要 ..................................................................................................................................... I
英文摘要 .................................................................................................................................. III
誌謝 ........................................................................................................................................... V
目錄 ........................................................................................................................................ VII
圖目錄 ....................................................................................................................................... X
表目錄 .................................................................................................................................... XV
第一章 簡介與研究動機 .......................................................................................................... 1
1-1 微電子元件之熱管理 .................................................................................................. 1
1-2 致冷技術之簡介 .......................................................................................................... 1
I. 被動致冷技術 ................................................................................................ 2
II. 主動致冷技術 ................................................................................................ 2
1-3 熱電致冷元件原理 ................................................................................................... 2
I. 熱電效應-帕爾帖效應（Peltier effect） ...................................................... 3
II. 熱電優值（Figure of merit，ZT） ............................................................... 3
III. 熱電致冷元件之指標 .................................................................................... 4
IV. 熱電致冷元件之發展 .................................................................................... 4
1-4 研究動機 ..................................................................................................................... 6
第二章 矽鍺微熱電致冷元件之製程開發 ............................................................................ 14
VIII
2-1 前言 ............................................................................................................................ 14
2-2 矽鍺柱陣列之製程 .............................................................................................. 14
I. 矽鍺柱陣列之蝕刻條件 .............................................................................. 14
II. 矽鍺柱陣列之製程開發 .............................................................................. 15
2-3 N 型與P 型矽鍺柱之離子佈植相關製程 ................................................................ 16
I. N 型與P 型矽鍺柱之離子佈植條件 .......................................................... 16
II. 離子佈植阻擋層-ma-N 2403 光阻之去除 .................................................. 16
2-4 矽鍺柱間之金屬連結定義 ....................................................................................... 17
I. 以NiSi 作為N 型與P 型矽鍺柱底部連結 ................................................ 17
II. 以掀離方式（Lift-off）製作N 型與P 型矽鍺柱頂部鋁連結 ................. 18
第三章 矽鍺微熱電致冷元件完整製程 ................................................................................ 30
3-1 前言 ............................................................................................................................ 30
3-2 矽鍺微熱電致冷元件製程 ....................................................................................... 30
I. 薄膜沉積 ...................................................................................................... 30
II. 離子佈植（P 型） ....................................................................................... 30
III. 定義熱電致冷單位元（Cell） ................................................................... 31
IV. 結構帄坦化 .................................................................................................. 31
V. 回蝕Si3N4 與沉積TEOS SiO2 .................................................................... 31
VI. 定義ma-N 2403 光阻以利N 型離子佈植 ................................................. 32
IX
VII. 去除經離子佈植轟擊之ma-N 2403 光阻與定義Pillar ............................ 32
VIII. Si3N4 沉積作為矽鍺柱側壁 ....................................................................... 33
IX. 定義底部溫度感測金屬線放置之區域與佈植離子活化 .......................... 33
X. 連結微熱電致冷元件底部之NiSi 電極製作 ............................................. 34
XI. 以掀離製程製作微熱電致冷器之連結 ...................................................... 34
XII. BMR SiO2 沉積作為鋁連結之保護層 ........................................................ 34
XIII. 定義溫度感測金屬線（Al） ...................................................................... 35
第四章 熱電致冷元件量測方式與數據分析 ........................................................................ 45
4-1 溫度量測方式 ........................................................................................................... 45
I. 熱電偶計量測法 .......................................................................................... 45
II. 紅外線攝影量測法 ...................................................................................... 45
III. 金屬線阻值量測法 ...................................................................................... 45
4-2 元件內部電阻效應 ................................................................................................... 46
4-3 熱電致冷元件量測 ................................................................................................... 47
I. 溫度感測金屬線之電阻溫度係數計算（Temperature Coefficient Resistance）
47
II. 矽鍺微熱電致冷元件量測與分析 .............................................................. 48
第五章 總結與未來展望 ........................................................................................................ 61
參考資料 .................................................................................................................................. 62參考文獻 [1] Edward J. Correia, Sorry, Moore’s Law: Multicore Is The New Game In Town, 2011, from
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19th IEEE SEMI-THERM Symposium, pp. 61-65, 2003.指導教授 李佩雯 審核日期 2013-11-20 推文 plurk
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