注入鎖定除頻器之研究及其鎖相迴路應用

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林宗憲(Tsung-Hsien Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

注入鎖定除頻器之研究及其鎖相迴路應用
(Research on Injection-Locked Frequency Divider and Its Phase-Locked Loop Application)

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摘要(中)

本論文主要針對應用於微波與毫米波鎖相迴路之注入鎖定技術。第二章與第三章分別闡述應用於鎖相迴路中的注入鎖定除頻器及其鎖相迴路應用。第四章為注入鎖定振盪器的電路設計與量測結果。
第二章介紹各類除頻器架構以及設計原理，並且提出注入鎖定除六與除五除頻器對鎖定頻寬的理論模型，從理論模型分析得知，鎖定頻寬跟注入器(injector)的元件與注入訊號大小成正比。同時採用台積電提供的90 nm低功耗互補式金氧半場效電晶體製程(TSMC 90 nm LP CMOS)實現注入鎖定除六除頻器，量測最大鎖定頻寬為2.9 GHz。第三章是將第二章所提出之除六除頻器整合至鎖相迴路系統，並且討論外在環境對量測電路的影響，提出實質的解決方案。同樣是使用台積電提供的90 nm製程實現，鎖相迴路的鎖定頻寬為25.3~27.3GHz，輸出功率接大於-8 dBm。在鎖定頻率為25.38 GHz，在距離中心頻10 kHz、100 kHz與1 MHz下，分別為-86.4、-90.7與-91.69 dBc/Hz。電路直流總功耗為40 mW，達到低直流功耗的效果。
第四章提出一個使用基級注入鎖定振盪器。藉由調整閘極端的電壓與基級注入鎖定技術，改善輸出相位雜訊與鎖定頻寬。使用台積電提供的90 nm製程實現，在振盪頻率為50 GHz、60 GHz與70 GHz下，有最寬的鎖定頻寬百分比分別為7.8%、13.8%與14.7%，總直流功耗為31.2~44.4mW。

摘要(英)

This thesis focuses on the injection-locked technique for the microwave and millimeter-wave phase-locked loop (PLL). A Ka-band injection-locked frequency divider (ILFD) and its PLL application are presented in Chapter 2 and 3, respectively. Finally, The design and analysis results of a V-band injection-locked oscillator (ILO) are proposed in Chapter 4.
Several frequency dividers and the injection-locked theory are introduced in Chapter 2. The locking range of divide-by-6 and divide-by-5 ILFDs is investigated to obtain the design methodology. From the analysis, the locking range of ILFDs is proportional to the device size of the injectiors and the amplitude of the injection signal. The proposed divide-by-6 ILFD is fabricated using TSMC 90 nm low power (LP) CMOS process and it features with a locking range of 2.9 GHz. Moreover, the proposed divide-by-6 ILFD is applied to a fully integrated Ka-band PLL. Several DC bypass networks for the measurement is discussed to further reduce the baseband /DC noise, and the effective solution is also addressed. The measured output phase is -86.4, -90.7, and -91.69 dBc/Hz at 10 kHz, 100 kHz, and 1 MHz offset at 25.38 GHz. The total DC consumption of PLL is about 40 mW.
The proposed injection-locked oscillator using TSMC 90 nm LP CMOS process is presented in Chapter 4. With the body-injection technique, wider locking range can be achieved. As the oscillation frequency are 50, 60, and 70 GHz, the widest locking ranges percentage at 7.8%, 13.8% and 14.7%, respectively. The total DC power consumption is about 31.2~44.4 mW.

關鍵字(中)

★ 鎖相迴路
★ 注入鎖定
★ 頻率除頻器
★ 除六
★ 振盪器

關鍵字(英)

★ Phase-locked loop
★ injection-locked
★ frequency divider
★ divide-by-6
★ oscillator

論文目次

摘要 I
Abstract II
目錄 III
圖目錄 VI
表目錄 XIII
第一章緒論 1
1.1 研究動機及背景 1
1.2 現況研究及發展 2
1.3 貢獻 2
1.4 論文架構 3
第二章應用於Ka頻段注入鎖定除頻器 4
2.1 簡介 4
2.2 除頻器架構概述 4
2.2.1 單真一相位時序(TSPC)除頻器[60] 5
2.2.2 電流模式邏輯(CML)除頻器[61] 6
2.2.3 米勒(Miller)除頻器[62] 8
2.2.4 注入鎖定原理與除頻器 9
2.2.4.1 注入鎖定原理概述[64] 9
2.2.4.2 注入鎖定(ILFD)除頻器 13
2.3 注入鎖定除頻器頻寬分析 14
2.3.1 分析電路模型簡介[39] 14
2.3.2 注入鎖定除六除頻器鎖定頻寬分析 15
2.3.2.1 電路架構與模型 15
2.3.2.2 Q值分析 17
2.3.2.3 注入電流與振盪電流 18
2.3.2.4 輸入阻抗討論 22
2.3.2.5 鎖定頻寬 24
2.3.3 注入鎖定除五除頻器鎖定頻寬分析 25
2.3.3.1 電路架構分析 25
2.3.3.2 注入電流迴路一分析 27
2.3.3.3 注入電流迴路二分析 29
2.3.3.4 鎖定頻寬分析 32
2.3.4 分析結果與討論 34
2.4 Ka頻段注入鎖定除六除頻器 35
2.4.1 高除數預除器架構簡介[72] 35
2.4.2 電路設計 36
2.4.3 實驗結果與討論 41
2.5 總結 49
第三章 Ka頻段鎖相迴路 51
3.1 簡介 51
3.2 壓控振盪器 52
3.3 除頻器 54
3.4 相位頻率偵測器 56
3.5 電荷幫浦 57
3.6 迴路濾波器與迴路分析 61
3.7 電路實現及實驗結果與討論 65
3.8 除錯與量測改進方法 72
3.9 總結 83
第四章基極注入鎖定振盪器 85
4.1 簡介 85
4.2 注入鎖定振盪器概述 86
4.3 鎖定頻寬分析[92] 88
4.4 電路設計 90
4.5 實驗結果與討論 92
4.6 除錯與量測結果討論 102
4.7 總結 104
第五章結論 106
附錄 : 相位陣列接收機量測 107
A.1 TSMC LP 90 nm CMOS V頻段單、雙路相位陣列電路 107
A.1.1 低雜訊放大器 107
A.1.1 正交調變器[107] 110
A.1.3 閘極驅動達靈頓混波器 111
A.4 V頻段單、雙路相位陣列電路模擬與量測結果 112
A.2 WIN GaAs 0.5 μm E/D-mode PHEMT Ka頻段四路相位陣列電路 121
A.2.1 低雜訊放大器 121
A.2.2 正交向量調變器 124
A.2.3 閘極驅動達靈頓混波器 126
A.2.4 Ka頻段四路相位陣列模擬與量測結果 127
A.3 總結 133
參考文獻 135

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指導教授

張鴻埜(Hong-Yeh Chang)

審核日期

2013-12-23

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