鐵電可變電容之設計與製作

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姓名

陳昫丞(Shiu-Cheng Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

鐵電可變電容之設計與製作
(Design and Fabrication of Ferroelectric Varactors)

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摘要(中)

鐵電可變電容具有高電容密度、高可調度、低操作電壓及較低的製程複雜度等優點。在本研究中，我們設計兩種基於鈦酸鍶鋇薄膜的平行板電容結構、發展其製作流程，並量測其特性。
第一種鐵電平行板電容結構以Pt下電極定義出電容之寬度，以Pt/Au上電極定義出電容之長度，中間夾層為鈦酸鍶鋇薄膜。此結構製作流程單純，僅需三道光罩。我們在數個製程梯次中基於此結構製作鐵電平行板電容；在本論文中，我們描述其中四個梯次的量測結果。此結構之鐵電平行板電容在偏壓6–7 V時可達到2:1的可調度，而電容之崩潰電壓約在7 V左右。量測得之電容密度最高約為20 fF/µm2；於2.4 GHz下、偏壓為0 V時，其品質因子約在15左右。
雖然前述之平行板電容結構具有製程單純之優點，但其崩潰電壓偏低，如此將限制其容值變化之範圍。崩潰電壓低通常是由於薄膜的階梯覆蓋能力不佳；為解決此問題，我們設計了第二種鐵電平行板電容結構。在第一種結構中，上下電極交曡的階梯區域之間為鈦酸鍶鋇薄膜；在第二種結構中，則將之取代為崩潰電場較高且階梯覆蓋能力的氮化矽薄膜。此結構之製程共需五道光罩。量測結果顯示，崩潰電壓可由原本的7 V提升至14 V。此鐵電可變電容偏壓在5 V時可以達到2:1的可調度，偏壓在12 V時可以達到3:1的可調度。電容密度最高約為19 fF/µm2；於1.8 GHz下、偏壓為0 V時，品質因子可達20以上。
我們成功地發展了兩種鐵電可變電容結構之製作流程，並比較其量測結果。第一種電容結構具有製程單純之優點，第二種電容結構則具有較高的崩潰電壓。藉由製程之改良，崩潰電壓可提升為兩倍，大幅地增進了鐵電可變電容的實用性。

摘要(英)

Ferroelectric varactor has the advantages of high capacitance density, high tunability, low operating voltage, and low complexity in fabrication. In this research, we have designed two different types of capacitor structures for parallel-plate capacitors based on barium-strontium-titanate (BST) thin films, developed the fabrication flows, and characterized the performance of the ferroelectric varactors.
The first capacitor structure has its width and length defined by the Pt bottom electrode and Pt/Au top electrode, respectively, with BST thin film as the insulating layer stacking in between the top and bottom electrodes. Fabrication complexity of this structure is low as only three masks are required. We have fabricated ferroelectric parallel-plate capacitors based on this capacitor structure in several fabrication runs. In this thesis, we describe the measurement results of the ferroelectric varactors produced in four of these runs. Measurement results show that, 2:1 tunability can be reached under a bias voltage of 6–7 V for the ferroelectric varactors based on the first capacitor structure. The breakdown voltage of the varactors is about 7 V. The maximum capacitance density is approximately 20 fF/µm2. Under 0-V bias, the quality factor at 2.4 GHz is about 15.
Though the former capacitor structure has the advantage of simple fabrication flow, the breakdown voltage of the ferroelectric varactor based on it is low, which limits the capacitance tuning range. Low breakdown voltage is usually due to the step coverage of thin films is poor. To solve this problem, the second type of capacitor structure is designed. In the first type of capacitor structure, it is the BST thin film that presents at the step where bottom and top electrodes overlap. In the second type of capacitor structure, the BST thin-film at the step is replaced by silicon-nitride thin film, which possesses higher breakdown field and better step coverage capability. Five masks are required to fabricate ferroelectric capacitors based on this capacitor structure. Measurement result shows that the breakdown voltage is improved from the original 7 V to 14 V. The tunability reaches 2:1 and 3:1 at bias voltage of 5 V and 12 V, respectively. The maximum capacitance density is around 19 fF/µm2. Under 0-V bias, the quality factor at 1.8 GHz is greater than 20.
We have successfully developed the fabrication flows for two types of capacitor structures for ferroelectric varactors and compared the measurement results. The first capacitor structure favors simple fabrication process whereas the second possesses high breakdown voltage. Through the advance of the fabrication process, the breakdown voltage is increased by a factor of two, which greatly enhances the practicability of the ferroelectric varactors

關鍵字(中)

★ 鐵電可變電容

關鍵字(英)

★ Ferroelectric Varactors

論文目次

摘要I
AbstrateII
誌謝IV
目錄V
第一章緒論1
1–1研究動機1
1–2可變電容技術簡介2
1–3鐵電材料特性4
1–4章節介紹6
第二章鐵電平行板電容7
2–1簡介7
2-2鐵電平行板電容光罩設計8
2–3鐵電平行板電容製作流程12
2–3–1下電極製作流程12
2–3–2鐵電薄膜沉積原理及條件16
2–3–3鐵電薄膜介電層製作流程18
2–3–4上電極製作流程20
2–4鐵電平行板電容量測結果25
2–4–1第000梯量測結果30
2–4–2第001梯量測結果36
2–4–3第002梯量測結果42
2–4–4第003梯量測結果48
2–5結果與討論54
第三章高崩潰電壓之鐵電平行板電容56
3–1簡介56
3–2高崩潰電壓之鐵電平行板電容光罩設計58
3–3高崩潰電壓之鐵電平行板電容製作流程62
3–3–1下電極製作流程與鐵電薄膜沉積62
3–3–2上電極製作流程64
3–3–3鐵電薄膜介電層製作流程66
3–3–4氮化矽保護層之沉積與製作流程68
3–3–5接腳層（pad）製作流程71
3–4高崩潰電壓之鐵電平行板電容量測結果73
3–4–1第004梯編號Si3N4–1量測結果77
3–4–2第004梯編號Si3N4–2量測結果83
3–5結果與討論89
第四章結論90
4–1結果與討論90
4–2未來研究方向92
參考文獻93
附錄95

參考文獻

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指導教授

傅家相(Jia-Shiang Fu)

審核日期

2013-11-4

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