二維無接面雙閘極場效電晶體之空乏特性探討

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姓名

蘇翊凱(Yi-Kai Su) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

二維無接面雙閘極場效電晶體之空乏特性探討
(Depletion Characteristics Investigation of 2D Junctionless Double-Gate MOSFETs)

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摘要(中)

在本篇論文中，首先先介紹無接面雙閘極場效電晶體的優點，我們以二維空間概念建立了完整的元件模型，並利用元件的能帶觀念導入主題。當元件所外加的閘極電壓不同時，元件會產生什麼樣的反應，若閘極電壓過大，則元件通道內會產生聚集現象，與傳統場效電晶體的反轉現象是不同的，因此我們做了一番的比較。同時也使用半導體物理觀念推導出臨限電壓公式，再由臨限電壓公式推導出空乏層大小，且使用兩種簡化方法推導出近似的電流方程式，然後都加以模擬比較，驗證其公式的精準度。並探討元件通道內的電荷分佈，著重於當元件在聚集現象時，若輸入汲極電壓產生電流，聚集電荷是否會明顯地影響電流值。

摘要(英)

In this thesis, at first we introduce the advantages of junctionless double-gate MOSFET. We establish two-dimensional device model for numerical simulation, and use the energy band diagram to study the device. When the applied gate voltage increases for an n-channel device, the n-channel will be in forward bias. When the gate voltage is too large, the n-channel will be in accumulation mode. It is different from the traditional MOSFET’s which is operated in inversion mode for a large gate bias. We make some comparison between these two MOSFET’s. Furthermore, we also derive the threshold voltage by using semiconductor physics, then use the threshold voltage to derive the depletion layer’s thickness, and find two simplified methods to derive the approximate drain current. Finally, we compare the current equations with the result obtained from 2D numerical simulation to verify the accuracy. We study the charge distribution in the device channel, and focus on the accumulation charge effect to the drain current.

關鍵字(中)

★ 無接面
★ 無接面場效電晶體
★ 無接面雙閘極場效電晶體

關鍵字(英)

★ Junctionless
★ Junctionless MOSFETs
★ Junctionless Double-Gate MOSFETs

論文目次

摘要 I
Abstract II
目錄 III
圖目錄 V
表目錄 VII
第一章　簡介 1
第二章　雙閘極無接面MOSFET之元件模型 3
2-1　二維等效模擬電路 3
2-2　元件結構 4
2-3　研究動機 5
第三章　雙閘極無接面MOSFET之工作原理 9
3-1　Junctionless MOSFET能帶 9
3-2　臨限電壓推導 13
3-3 空乏層大小推導 16
3-4 模擬驗證臨限電壓 18
3-5 臨限電壓之調變 20
3-6　模擬驗證空乏層大小 23
3-7　源極端與汲極端之通道空乏層對元件影響 26
第四章　雙閘極無接面MOSFET之電流特性 32
4-1　Junctionless MOSFET之電流方程式推導 32
4-2　電流方程式驗證 37
4-3　聚集現象之電流值分析 39
第五章　結論 41
參考文獻 42

參考文獻

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[2] S. M. Sze, “Semiconductor Device：Physics and Technology,” 2^nd Edition, Wiley & Sons Inc, Chapter 6, 2002.
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[7] Zhuojun Chen, Yongguang Xiao, Minghua Tang, Ying Xiong, Jianqiang Huang, Jiancheng Li, Xiaochen Gu, and Yichun Zhou, “Surface-Potential- Based Drain Current Model for Long-Channel Junctionless Double-Gate MOSFETs,” IEEE Transactions on Electron Devices, vol. 59, no. 12, pp.3292-3298, 2012.
[8] A. Kranti, R. Yan, C.-W. Lee, I. Ferain, R. Yu, N. Dehdashti Akhavan, P. Razavi, J.-P. Colinge, “Junctionless Nanowire Transistor (JNT): Properties and Design Guidelines,” IEEE, pp.357-360, 2012.
[9] J.P. Duarte, Sung-Jin Choi, Dong-Il Moon, and Yang-Kyu Choi, “Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors,” IEEE Electron Device Letters, vol. 32, no. 6, pp.704-706, 2011.
[10] Juan Pablo Duarte, Sung-Jin Choi, and Yang-Kyu Choi, “A Full-Range Drain Current Model for Double-Gate Junctionless Transistors,” IEEE Transactions on Electron Devices, vol. 58, no. 12, pp.4219-4225, 2011.

指導教授

蔡曜聰(Yao-Tsung Tsai)

審核日期

2013-7-2

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