參考文獻 |
[1] W. T. Nye,E. Polak and A. Sangiovanni-Vincentelli, “DELIGHT: An optimization-based computer-aided design system,” IEEE International Symposium on Circuits and Systems,pp. 851-855, 1981.
[2] M. Hershenson, S. P.Boyd andT.H.Lee, “Automated design of folded-cascode op-amps with sensitivity analysis,” IEEE International Conference on Electronics, Circuits and Systems, vol.1, pp.121-124,1998.
[3] L. Dai and R. Harjani, “CMOS switched-op-amp-based sample-and-hold circuit,” IEEE Journal of Solid-State Circuits, vol.35, no.1, pp. 109-113, 2000.
[4] G. Espinosa-Flores-Verdad and R. Salinas-Cruz. “Symmetrically compensated fully differential folded-cascode OTA,” Electronic Letters. vol. 35, no. 19, pp. 1603-1604, 1999.
[5] M. Kayal, ”Transistor-Level Analog IC Design,” Short Course Lecture Note, EPFL, Lausanne, Switzerland, 2004.
[6] R. Hägglund, E. Hjalmarson, and L. Wanhammar, “Automatic DeviceSizing in Analog Circuit Design,”National Conference Radio Science(RVK), pp. 187-191, 2002.
[7] R. Hägglund, E. Hjalmarson, and L. Wanhammar, “Optimization-Based Device Sizing in Analog Circuit Design,” Swedish System-on-Chip Conference, Falkenberg, Sweden, 2002.
[8] E. Hjalmarson, R. Hägglund, and L. Wanhammar, “An Optimization-Based Approach for Analog Circuit Design,” European Conferenceon Circuit Theory Design, pp. 369-372, 2003.
[9] E. Hjalmarson, R. Hägglund, and L. Wanhammar, “A Design Platformfor Computer-Aided Design of Analog Amplifiers,”Swedish System-on-Chip Conference, Eskilstuna, Sweden, 2003.
[10] R. Hägglund, E. Hjalmarson, and L. Wanhammar, “A Design Path forOptimization-Based Analog Circuit Design,” The Midwest Symposium on Circuits and Systems, pp. 287–290, 2002.
[11] F. El-Turky and E.E. Perry, “BLADES: an arrificial intelligence approach to analog circuit design”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 6, pp. 680-692, 1989.
[12] J. Mahattanakul, J. Chutichatuporn, “Design Procedure for Two-Stage CMOS OpampWith Flexible Noise-Power Balancing Scheme,” IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 52, no. 8, pp. 1508-1514, 2005.
[13] C.-W. Lin, P.-D. Sue, Y.-T. Shyu, S.-J Chang, “A Bias-Driven Approach for Automated Design of Operational Amplifiers,” International Symposium on VLSI Design, Automation and Test , pp. 118-121, 2009.
[14] Y.-T.Shyu, C.-W. Lin, Jin-Fu Lin and Soon-Jyh Chang, “A gm/ID-based synthesis tool for pipelined analog to digital converters,” International Symposium on VLSI Design, Automation and Test, pp 299-30, 2009.
[15] P. Mandal, V. Visvanathan, “CMOS Op-Amp Sizing Using a Geometric Programming Formulation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 1, pp. 22-38, 2001.
[16] M.delM.Hershenson, S.P. Boyd, T.H.Lee, “Optimal design of a CMOS op-amp via geometric programming,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 1, pp. 1-21, 2001.
[17] M.H Maghami., F. Inanlou, R. Lotfi, “Simulation-Equation-Based Methodology for Design of CMOS Amplifiers Using Geometric Programming,” IEEE International Conference on Electronics, Circuits and Systems, pp.360-363, 2008.
[18] T. Kahookar Toosi, E. Zhian Tabasy, H. Sarbishaei, R. Lotfi, "ISECAD: An Iterative Simulation-Equation-Based Opamp-Design CAD Tool," IEEE International Symposium on Circuits and Systems, 2006.
[19] J. Yuan, N. Farhat, and J. Van der Spiegel, "GBOPCAD: a synthesis tool for high-performance gain-boosted opamp design," IEEE Transaction on Circuits and Systems-I, vol. 52, no. 8, pp.1535-1544, Aug. 2005.
[20] C. D. Perttunen, “A nonparametric global optimization method using the rank transformation,” IEEE Conference on Decision and Control, vol. 1, pp.888-893, Dec. 1989.
[21] C. D. Perttunen, “A computational geometric approach to feasible region division in constrained global optimization” IEEE International Conference on Systems, Man, and Cybernetics, vol. 1, pp.585-590, 1991.
[22] B.Razavi, “Design of analog CMOS integrated circuits”, McGraw-Hill Higher Education, 2001
[23] F. Silveira, D. Flandre, P.G.A. Jespers, ” A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA,” IEEE Journal of Solid-State Circuits, vol. 31, no. 9, pp. 1314-1319, 1996.
[24] W.Gao,R.Hornsey, “A power optimization method for CMOS op-amps using sub-space based geometric programming,” Design, Automation & Test in Europe Conference & Exhibition, pp. 508-513, 2010.
[25] 詹立宇,“可改善幾何演算法之精準度的電壓趨動運算放大器自動化設計方法,” 國立中央大學電機工程研究所碩士論文, July 2011
[26] 郭晉誠, “建立考慮電源雜訊之鎖相迴路行為模型” 國立中央大學電機工程研究所碩士論文, July 2005 |