DVB-T基頻發射機之FPGA硬體設計與實現

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：6

、訪客IP：3.15.190.144

姓名

陳德龍(Te-lung Chen) 查詢紙本館藏

畢業系所

通訊工程學系

論文名稱

DVB-T基頻發射機之FPGA硬體設計與實現
(Design and FPGA Implementation of Baseband Transmitter for DVB-T System)

相關論文

★ WiMAX基地台信號覆蓋實地量測與分析	★ 被動元件阻抗量測原理及實務
★ 正交分頻多工接收機中數位降頻器之低通濾波器設計	★ 適用於數位電視之里德所羅門編解碼硬體實作
★ 數位電視地面廣播系統之通道估測與等化器設計與實現	★ 數位電視地面廣播之數位基頻收發機即時軟體設計與實現
★ 數位電視地面廣播系統通道解碼之腓特比解碼器實現	★ 無線區域網路收發機之整合實現與測試
★ 以DSP處理器實現數位電視地面廣播系統發射機	★ 數位電視內接收機同步系統之設計與實現
★ AIS實體層(GMSK/FM)與資料鏈結層軟體無線電技術實現	★ 數位電視地面廣播系統內接收機之快速傅立葉轉換處理器研究與設計
★ 數位電視地面廣播之數位降頻器與再取樣器設計與實現	★ 軟體無線電任意基頻訊號接收機系統設計及實現
★ 陣列天線互耦及接收機增益與相位對波束合成器性能影響及校正研究	★ 適用於OFDM系統之可變長度快速傅立葉轉換處理器設計與實現

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

DVB-T(Digital Video Broadcasting - Terrestril)為歐洲廣播聯盟(European Broadcast Union，EBU)制定的數位電視廣播網路系統規格，也是台灣目前採用的數位電視廣播系統。

在本文中，我們採用目前台灣數位電視廣播的規格，設計並且實現DVB-T的基頻傳送端即時硬體實現以及使用FPGA進行驗證。發射端的硬體架構包含了以下的主要模組：里德-所羅門碼編碼器，外交錯器、迴旋碼編碼器、打孔器、內交錯器(bit、symbol)、快速反傅利葉處理器、循環前綴產生器以及生取樣器，設計問題方面有多速率運作模組間的整合與同步、快速反傅利葉處理器在定點數上的解析度以及低通濾波器在數位升取器的使用。

在設計階段上，我們首先使用MATLAB進行建模與分析，已獲得適當的系統性能/精準度以來估計硬體複雜度來獲得適當的設計。在實驗階段，Verilog硬體描述語言用於使用邏輯行為來描述其硬體架構與及時系統，時序模擬使用ModelSim，硬體驗證使用FPGA。

及時驗證於基頻發射機是經由此發射機發射一DVB-T訊號載上一較低的中頻載波後，經由電力線通道來實現與展示。及時發射機包含了FPGA以及數位類比轉換器及電力線通訊類比前級電路
。發射的DVB-T訊號經由另一個電力線通訊接收模塊收回後，以離線後以接收機的演算法來分析接收到的訊號。

摘要(英)

Digital Video Broadcasting–Terrestrial (DVB-T) is the digital television broadcasting standard specified by the European Broadcasting Union, which is also adopted in Taiwan.

In this thesis, we design and realize a real-time hardware baseband transmitter for DVB-T using FPGA. The architecture of the transmitter is comprised of the following main modules: Reed-Solomon code encoder, outer interleaver, convolutional code encoder with puncher, innner interleaver (bit, symbol), IFFT processor, Cyclic-Prefix generator and digital-upconverter. The design issues include interfacing/synchronization between multi-rate modules, fixed-point resolution of the IFFT processor and the lowpass filter in the digital-upconverter. In the design phase, we first use MATLAB for modeling and analysis to obtain an appropriate design which tradeoffs the system performance/accuracy with estimated hardware complexity. In the implementation phase, Verilog hardware description language is used for coding the hardware system followed by logic behavior and real-time verifications with ModelSim and FPGA platform, respectively.

The real-time verification of the baseband transmitter is achieved by a realization and demonstration of a real-time transmitter which transmits the DVB-T signal with a lower IF carrier through the power-line channel. The real-time transmitter comprises of the FPGA platform which is loaded with the transmitter design, the Digital-to-Ananlog module and the power-line communication (PLC) analog frontend. The transmitted DVB-T signal is captured by another PLC receiver platform and then is analyzed by off-line receiver algorithm which verifies the real-time transmitted signal.

關鍵字(中)

★ 數位電視廣播
★ 電力線通訊
★ 正交分頻多工
★ 現場可程式化邏輯陣列

關鍵字(英)

★ Digital Video Broadcasting
★ OFDM
★ Power Line Communication
★ FPGA

論文目次

中文摘要.............................................i
ABSTRACT ...........................................iii
謝誌.................................................v
目錄.................................................vii
圖目錄...............................................x
表目錄...............................................xix
一、緒論.............................................1
1.1 研究動機與背景....................................1
1.2 章節簡介.........................................2
二、數位電視地面廣播系統簡介............................3
2.1 正交分頻多工調變原理與技術..........................3
2.1.1 單載波調變與多載波調變及載波的正交性...............3
2.1.2 OFDM系統調變原理及數學模型.......................6
2.1.3 OFDM系統的優缺點................................13
2.2 DVB-T系統與規格簡介...............................15
2.2.1 DVB-T傳輸模式與比較.............................15
2.2.2 DVB-T系統與參數.................................16
2.2.3 DVB-T發射端簡介.................................17
三、數位電視調變器硬體架構..............................35
3.1 里德‧所羅門碼(Reed-Solomon Code，RS Code)..........36
3.2 外交錯器(Outer Interleaver).......................39
3.3 迴旋碼編碼器(Convolutional Code Encoder)...........42
3.4 串列轉並列(Serial To Parallel).....................45
3.5 位元交錯器(Bit Interleaver)........................48
3.6 符元交錯器(Symbol Interleaver).....................51
3.7 星座點映射器(QAM Mapping)..........................54
3.8 領航碼產生器(Pilot Generator)......................57
3.9 碼框擺放器(Fram Adaptation)........................60
3.10 快速反傅立葉轉換器(Invers Fast Fourier Transform)..63
3.10.1 FFT/IFFT模組復用................................65
3.10.2 蝶形運算器硬體架構...............................66
3.10.3 坐標軸數位旋轉計算器(CORDIC)演算法................68
3.10.4 旋轉因子產生單元.................................70
3.11 位元反轉排列(Bit Reversal Ordering，BRO)...........73
3.12 循環前綴產生器(Cyclic Prex，CP)....................76
3.13 多相位數位低通濾波器................................79
3.13.1 升頻取樣(Up Sampling)...........................79
3.13.2 數位低通濾波器...................................81
3.13.3 多相位濾波器(Poly-phase lter)....................89
3.14 並列轉串列(Parallel to Serial).....................94
3.15 載波乘法器(Carrier Mixer)..........................97
3.16 DBR out(DAC輸出機制)...............................101
3.17 子模組使用資源比較表................................104
3.18 DVB-T發射機合成報告................................105
四、硬體設計與實現.......................................106
4.1 硬體開發流程........................................107
4.2 FPGA驗證環境........................................108
4.3 發射端系統架構.......................................109
4.4 多速率模組系統整合....................................110
4.4.1 FIFO(First-In-First-Out).........................110
4.4.2 進出速率不同之模組設計..............................113
4.5 取樣率造成的模組速率設計限制...........................114
4.6 IFFT硬體輸出之向量訊號誤差............................117
4.7 取樣率同步問題.......................................119
4.7.1 取樣率偏移探討.....................................119
4.7.2 再取樣器原理.......................................122
4.8 傳收平台............................................124
4.9 傳輸環境............................................131
4.10 傳收結果...........................................132
4.10.1 發射訊號資訊與品質(4QAM)...........................133
4.10.2 發射訊號資訊與品質(16QAM)..........................136
4.10.3 發射訊號資訊與品質(64QAM)..........................142
4.10.4 示波器頻譜觀測.....................................144
4.10.5 DAC-ADC對接傳收結果(16QAM).........................148
4.10.6 DAC-ADC對接傳收結果(64QAM).........................152
4.10.7 經過電力線通道最近距離傳輸結果(16QAM).................156
4.10.8 經過電力線通道最近距離傳輸結果(64QAM).................160
4.10.9 辦公室環境(傳送接收端50m延長線最近點4QAM).............164
4.10.10辦公室環境(傳送接收端50m延長線最近點16QAM)............168
4.10.11辦公室環境(傳送接收端50m延長線最近點64QAM)............172
4.10.12辦公室環境(50m延長線+4.5m電力線16QAM)................176
4.10.13辦公室環境(50m延長線+4.5m電力線64QAM)................180
4.10.14辦公室環境(50m延長線+12.5m電力線16QAM)...............184
4.10.15辦公室環境(50m延長線+12.5m電力線64QAM)...............188
4.10.16辦公室環境(50m延長線+19.5m電力線16QAM)...............192
4.10.17辦公室環境(50m延長線+19.5m電力線64QAM)...............192
4.11 傳收結果總表.........................................196
五、結論..................................................197
參考文獻..................................................199

參考文獻

[1] E. ETSI, 300 744 digital video broadcasting (dvb); framing structure, channel
coding and modulation for digital terrestrial television," 2001.
[2] Y.-j. Hsiao, Channel measurement and transmitter implementation of power
line communications," 2013.
[3] M.-y. Hsu, Design and fpga implementation of baseband receiver for dvb-t
system," 2012.
[4] I. Tsai, Design and fpga implementation of sampling frequency oset synchro-
nization for dvb-t receiver in baseband," 2012.
[5] H. XIE and Z. SUN, The realization of polyphase decimation lter on fpga,"
Chinese Journal of Electron Devices, vol. 3, p. 019, 2012.
[6] J. Jiang, Design and FPGA Implementation of a Real-Time OFDM Transceiver
for Power Line Communications. PhD thesis, Master′s thesis, National Central
University, 2011.
[7] P.-C. Wang, Design and implementation of variable-length fast fourier trans-
form processor in ofdm systems," National Central University, 2007.
[8] W.-c. Lin, Synchronization for dvb-t in high-mobility environment," 2008.
[9] A. Majumder et al., Power line communications," Potentials, IEEE, vol. 23,
no. 4, pp. 4{8, 2004.
[10] R. Andraka, A survey of cordic algorithms for fpga based computers," in Pro-
ceedings of the 1998 ACM/SIGDA sixth international symposium on Field pro-
grammable gate arrays, pp. 191{200, ACM, 1998.
199
[11] S. He and M. Torkelson, A new approach to pipeline t processor," in Parallel
Processing Symposium, 1996., Proceedings of IPPS′96, The 10th International,
pp. 766{770, IEEE, 1996.
[12] M. Speth, S. A. Fechtel, G. Fock, and H. Meyr, Optimum receiver design for
wireless broad-band systems using ofdm. i," Communications, IEEE Transac-
tions on, vol. 47, no. 11, pp. 1668{1677, 1999.
[13] E. Berlekamp, Bit-serial reed-solomon encoders," Information Theory, IEEE
Transactions on, vol. 28, no. 6, pp. 869{874, 1982.
[14] S. He and M. Torkelson, Designing pipeline t processor for ofdm (de) mod-
ulation," in Signals, Systems, and Electronics, 1998. ISSSE 98. 1998 URSI
International Symposium on, pp. 257{262, IEEE, 1998.
[15] Y.-M. Chen and I.-Y. Kuo, Design of lowpass lter for digital down converter in
ofdm receivers," in Wireless Networks, Communications and Mobile Computing,
2005 International Conference on, vol. 2, pp. 1094{1099, IEEE, 2005.
[16] Y.-M. Chen, On the design of farrow interpolator for ofdm receivers with
asynchronous if sampling," in Communications and Networking in China, 2009.
ChinaCOM 2009. Fourth International Conference on, pp. 1{5, IEEE, 2009.
[17] N. Glover, Reed-solomon code encoder and syndrome generator circuit,"
Oct. 11 1988. US Patent 4,777,635.
200

指導教授

陳逸民(Yih-min Chen)

審核日期

2014-8-22

推文