博碩士論文 101521005 詳細資訊




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姓名 張光明(Guang-Ming Zhang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 無接面雙閘極電晶體與不同溫度下臨界電壓模擬
(Simulation of Double Gate Junctionless MOSFET and Temperature Dependence of Threshold Voltage)
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摘要(中) 本篇論文將利用C++的程式進行二維雙閘極無接面金氧半場效電晶體的模擬,模擬出其電壓與電流特性曲線與汲極電流。一開始,此論文將先在閘極電流與電壓的圖中討論臨界電壓與通道厚度與通道參雜濃度的關係,再藉由討論得結果決定最適合的臨界電壓。再決定臨界電壓後,需要模擬不同閘極電壓下的汲極電流以及汲極電流的開關比例,此模擬可以證實元件是否可以正常的運作以及模擬程式的正確性。在證實元件的正確性後,此論文將會模擬不同閘極電壓下的電壓電流特性曲線,並且將電流以數學公式的方式導出,進而驗證模擬與理論的值是否相同。此篇論文除了討論元件的基本電性,另外一個重點放在臨界電壓與溫度的關係上。此論文將會使用C++程式進行溫度的改變使其進而影響元件的基本電性。再模擬出臨界電壓與溫度的關係後,此論文將會參考文獻所實驗出的數值進行比較,比較是否有相同的特性,以確認其模擬是否正確。最後,此論文將會進行反向器的電路應用,將元件與電阻進行串連使其成一個反向器。並且量測出其參數進行確認電路的品質與特性。
摘要(英) This thesis uses the C++ to develop an adapted band matrix solver to simulate the I-V curve and the drain current of the 2-D double-gate n-channel MOSFET. And it discusses the threshold voltage from the I-Vg curve and selects the appropriate doping concentration and channel thickness to complete the following experiments. The I-Vg curve will be simulated to determine threshold voltage. The I-V curve can calculate drain current in different gate voltage. The results can be compared with the other reference papers. The depletion width can be obtained as an analytical equation. The analytical depletion width can be verified by the 2-D simulation. The 2-D simulation also verifies the result with the drain current equation which is obtained by Poisson’s equation. The equations of the threshold voltage can be developed, and the threshold voltage of double-gate n-channel MOSFET can be calculated. Afterword, this paper will simulate and discuss the correction between threshold voltage and temperature. This paper will include the thermal voltage and intrinsic doping concentration of temperature in the C++ program. After simulating, the value of simulation will be compared with the value of the reference paper to confirm the trend of threshold voltage. For circuit application, an inverter including a double-gate n-channel MOSFET and a 100 kΩ resistor will be used to simulate the Vo-Vi characteristics and analyzes the parameters of the inverter, and the noise margin will be calculated in order to determine the inverter’s performance and quality.
關鍵字(中) ★ 雙閘極無接面電晶體
★ C++
★ 元件模擬
★ 臨界電壓
關鍵字(英) ★ Double gate junctionless MOSFET
★ C++
★ Device simulation
★ Threshold voltage
論文目次 Chinese abstract ……………………………………………………………… i
Abstract ……………………………………………………………… ii
List ……………………………………………………………… iii
List of figures ……………………………………………………………… iv
List of tables ……………………………………………………………… v

Chapter 1. Introduction 1
1-1 The basic simulation of the double gate junctionless MOSFET 1
1-2 The advanced simulation application of the double gate junctionless MOSFET 3

Chapter 2. The structure and principle of double gate junctionless MOSFET 4
2-1 The structure of the double gate junctionless MOSFET 4
2-2 The work principle of the double gate junctionless MOSFET 6
2-3 The energy band of the double gate junctionless MOSFET 9
2-4 The threshold voltage of the double gate junctionless MOSFET 13

Chapter 3. The temperature dependence of threshold voltage in double gate junctionless MOSFET 16
3-1 The characteristic of P-N diode in different temperature 16
3-2 The theory and equation of the threshold voltage with temperature 18
3-3 The reference data of threshold voltage with temperature 21

Chapter 4. The experiment, the simulation result and the application 25
4-1 The basic simulation of the double gate junctionless MOSFET 25
4-2 The circuit application of the double gate junctionless MOSFET 30
4-3 Temperature dependence of the threshold voltage 32

Chpater 5. Conclusion 36
5-1 The basic simulation of the double gate junctionless MOSFET 36
5-2 The application and advanced simulation of double gate junctionless MOSFET 37

Reference paper 38 iv

List of Figures

Fig. 1 Structure of 2-D p-channel junctionless MOSFET. p.5
Fig. 2 The channel of the junctionless MOSFET is cut off by the depletion region. p.6
Fig. 3 The channel of the junctionless MOSFET reaches pinch off point. p.7
Fig. 4 The channel of double gate junctionless MOSFET takes shape. p.7
Fig. 5 At the more positive voltage, the channel will be without depletion layer, and the current is largest. p.8
Fig. 6 Subthreshold mode. p.9
Fig. 7 Threshold mode. p.10
Fig. 8 Conduction mode. p.10
Fig. 9 Flat band mode. p.11
Fig. 10 Accumulation mode. p.12
Fig. 11 The build-in voltage with different temperature. p.17
Fig. 12 The comparison of the depletion region in the normal and high temperature. p.19
Fig. 13 The fitting line of threshold voltage with temperature. p.20
Fig. 14 The I-V curve in difference temperature of the junctionless MOSFET. p.21
Fig. 15 The function of the threshold with the temperature. p.22
Fig. 16 The drain current with different temperature. p.23
Fig. 17 The function of the drain current with different temperature. p.23
Fig. 18 Threshold voltages with different doping concentration. p.26
Fig. 19 Threshold voltage with different thickness. p.26
Fig. 20 The on-off current of double gate junctionless MOSFET. p.27
Fig. 21 The I-V curve of double gate junctionless MOSFET. p.28
Fig. 22 Electrical potential versus different axis. p.29
Fig. 23 Inverter circuit. p.31
Fig. 24 The threshold voltage with the different temperature. p.32
Fig. 25 The function of the threshold voltage with temperature. p.33
Fig. 26 The drain current with different temperature when the gate voltage is 0.7 V. p.34
Fig. 27 The drain current with different temperature when the gate voltage is 0.8 V. p.35
Fig. 28 The drain current with different temperature when the gate voltage is 0.9 V. p.35

List of Tables

Table 1.
The values of the thermal voltage and the intrinsic doping concentration in different temperature. p.19
Table 2.
Simulation result compare with analytical model. p.28
Table 3.
The parameters of the inverters. p.31
Table 4. The threshold voltage with temperature. p.33
參考文獻 [1] J.-P. Colinge, C.-W. Lee, A. Afzalian, N. Dehdashti Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
[2] A. Kranti, R. Yan, C.-W. Lee, I. Ferain, R. Yu, N. D. Akhavan, P. Razavi, and J.-P. Colinge, “Junctionless nanowire transistor (JNT): Properties and design guidelines,” in Proc. ESSDERC, Sep. 14–16, 2010, pp. 357–360.
[3] S. Gundapaneni, S. Ganguly, and A. Kottantharayil, “Bulk planar junctionless transistor (BPJLT): An attractive device alternative for scaling,” IEEE Electron Device Lett., vol. 32, no. 3, pp. 261–263, Mar. 2011.
[4] Y. Taur and T. H. Ning, Modern VLSI Devices, 2nd ed., Cambridge, U.K.: Cambridge Univ. Press, 2009, p. 530.
[5] J. P. Duarte, S.-J. Choi, D.-I. Moon, and Y.-K. Choi, “Simple analytical bulk current model for long-channel double-gate junctionless transistors,” IEEE Electron Device Lett., vol. 32, no. 6, pp. 704–706, Jun. 2011.
[6] Y. Taur, X. Liang, W. Wang, and H. Lu, “A continuous, analytic draincurrent model for DG MOSFETs,” IEEE Electron Device Lett., vol. 25, no. 2, pp. 107–109, Feb. 2004.
[7] J.-M. Sallese, N. Chevillon, C. Lallement, B. Iniguez, and F. Pregaldiny, “Charge-based modeling of junctionless double-gate field-effect transistors,” IEEE Trans. Electron Devices, vol. 58, no. 8, pp. 2628–2637, Aug. 2011.
[8] J. P. Duarte, S.-J. Choi, and Y.-K. Choi, “A full-range drain current model for double-gate junctionless transistors,” IEEE Trans. Electron Devices, vol. 58, no. 12, pp. 4219-4225
[9] G.-M. Zhang, Y.-K. Su, H.-Y. Hsin,and Y.-T. Tsai, “Double gate junctionless MOSFET simulation and comparison with analytical model,” IEEE RSM Proc. Sep. 2013.
[10] C.-W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J.-P. Colinge, “High-temperature performance of silicon junctionless MOSFETs,” IEEE Transactions on Electron Devices, vol. 57, no. 3, March 2010.
[11] G. Groeseneken, J.-P. Colinge, H. E. Maes, J. C. Alderman, and S. Holt, “Temperature dependence of threshold voltage in thin-film SOI MOSFET’s,” IEEE Electron Device Letter, vol. 11, no. 8, August 1990.
[12] Y.-K. Su, Y.-T. Tsai “Depletion characteristics investigation of 2D junctionless double-gate MOSFETs,” Institue of Electrical Engineer National Central University June 2013.
指導教授 蔡曜聰(Yao-Tsung Tsai) 審核日期 2014-7-1
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