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姓名	侯泰安(Tai-an Hou)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	二維梯形模組在半導體元件模擬之驗證與探討 (Verification of 2D Trapezoid Element in Semiconductor Device and Comparasion with its Simplified Method)
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摘要(中)	本篇論文中，在探討與開發改良式梯形網格並且應用於環繞式閘極 MOSFET 模擬相關特性。為了探討其元件特性，我們運用基礎半導體理論波松方程式、電子連續方程式與電洞連續方程式，建構出2D梯形模組進行模擬。為了改善一般梯形網格在大角度時會使外心超出邊界造成的嚴重的誤差，所以研發出簡化版梯形模型來改善這個缺點，，並也將模擬結果與理論做比較，驗證其正確性，最後在使用新開發出的模型製作出MOS-Capacitor來量測出VTH 。
摘要(英)	This thesis explores and develops an improved trapezoid mesh and applies it to the 2D simulation of surrounding gate MOSFET. We use Poisson′s equation, electron continuity equation and hole continuity equation to construct a trpezoid Element mesh for 2D numerical simulation. The circumcentre will exceed the boundary in the large angle. The phenomenon will cause a serious mistake. For improving this problem, the simple model of circumcentre is developed. We also verify the simulation result with the theory. Finally, the use of newly developed models to produce a MOS-Capacitor to measure the VTH .
關鍵字(中)	★ 梯形網格 ★ 2D網格 ★ 環繞式閘極 ★ 模擬	關鍵字(英)	★ Trapezoid mesh ★ Simulation ★ Gate-All-Around
論文目次	摘要 II ABSTRACT III 圖目錄 IV 表目錄 V 第一章 簡介 1 第二章 二維元件梯形元件模擬架構及特性 3 2-1二維梯形網格結構定義 3 2-2簡化版梯形網格 10 第三章 二維梯形模組之驗證與比較 13 3-1二維園柱電阻驗證推導 13 3-2梯形模組的驗證 16 3-3簡化版梯形模組的驗證 20 第四章 圓柱形MOS-Capacitor之二維模擬與分析 23 4-1簡介環繞式閘極MOSFET 23 4-2簡化版梯型模型MOS-Capacitor 的VTH 之比較 27 第五章 結論 37 Reference 39
參考文獻	[1] H. IWAI, M. R. PINTO, C. S. RAFFERRY, J. E. ORISTIAN, R. W. DUTTON, "Velocity situation effect on short‐channel MOS transistor capacitance," IEEE [2] P. P. Wang, "Device MOSFET′s," IEEE Transactions on Electron Devices, vol ed ‐25, no.7, 1978. [3] T. Saito, T. Saraya, T. Inukai, H. Majimi, T. Nangumo, T. Hiramoto, "Suppression of Short Channel Effect in Triangular Parallel Wire Channel MOSFETs," IEICE Trans. on Electronics, vol. E85-C, no. 5, pp. 1073-1078, 2002. [4] J. Y. Song, W. Y. Choi, J. H. Park, J. D. Lee, and B.-G. Park, "Design Optimization of Gate-All-Around (GAA) MOSFETs," IEEE Trans. on Nanotechnology, vol. 5, no. 3, pp. 186-191, 2006. [5] N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, "High-Performance Fully Depleted Silicon Nanowire (Diameter 5 nm) Gate-All-Around CMOS Devices," IEEE Electron Device Letters, vol. 27, no. 5, pp. 383-386, 2006.′ [6] Y. S. Tso, "Analysis and simulation cylindrical coordinates of curved PN junction properties," Electrical Engineering Natl. Central Univ, Chung-Li city, Taiwan, R.O.C., 2010. [7] D. K.Cheng, Field and wave electromagnetics, 2nd ed.: Addison-Wesley Publishing Company , Inc., 1989. [8] J. Y. Peng, "Current Characteristic and Electric-field Analysis in 2-D SOI Semiconductor Devise Simulation," Electrical Engineering Natl. Central Univ, Chung-Li city, Taiwan, R.O.C., 2008. [9] D. A. Neamen, Semiconductor physics and devices, 3rd ed.: McGraw-Hill Companies, 2003. [10] J. He, et al., "Equivalent function transformation: a semi-empirical analytical method for predicting the breakdown characteristics of cylindrical- and spherical-abrupt PN junctions," Solid-State Electronics, vol. 44, pp. 2171-2176, Dec 2000. [11] B. Iniguez, et al., "Two-dimensional analytical threshold voltage roll-off and subthreshold swing models for undoped cylindrical gate all around MOSFET," Solid-State Electronics, vol. 50, pp. 805-812, May 2006. [12] K. Castellani-Coulie, et al., "Investigation of 30 nm gate-all-around MOSFET sensitivity to heavy ions: A 3-D simulation study," Ieee Transactions on Nuclear Science, vol. 53, pp. 1950-1958, Aug 2006. [13] C. C. Hu, Modern Semiconductor Devices for Integrated Circuits,2010 [14] N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, "High-Performance Fully Depleted Silicon Nanowire (Diameter 5 nm) Gate-All-Around CMOS Devices," IEEE Electron Device Letters, vol. 27, no. 5, pp. 383-386, 2006.′ [15] S. M. Sze, Physics of Semiconductor Devices: John Wiley & Sons Inc., 2006. [16] C. C. Hu, Modern Semiconductor Devices for Integrated Circuits,2010 [17] R. Yan et al., IEEE Trans electron Dev, 39, p. 1704 (1992) [18] K. Suzuki et al., IEEE Trans electron Dev, 40, p. 2326 (1993)
指導教授	蔡曜聰(Yao-Tsung Tsai)	審核日期	2014-7-1
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