||The operation of the tunnel field effect transistors (TFETs) can be carried out with a small operating voltage (0.5 V or less). Advantages of TFETs include excellent switching characteristics, low subthreshold slope (S.S.), and low power consumption. Although Silicon based TFETs have been developed but the power consumption and operation of the bias are high due to large bandgap of Silicon materials. Because Indium based TFETs show a lower effective tunneling barrier height (Ebeff), which results in lower operating bias voltage. Therefore, Indium based TFETs are studied in this thesis.|
For a typical p-i-n InGaAs material was used in this study, which is lattice matched to InP substrate., In order to achieve the tunneling operation of n-type TFET, a heavily doped p+-InGaAs is dedicated for source, n+-InGaAs is for drain, and undoped InGaAs is for channel. The tunneling junction for n-type TFET is located at the junction between p+ In0.53Ga0.47As (Be doping of 3.3 × 1019 /cm3) and undoped In0.53Ga0.47As. The channel is a 150 nm undoped In0.53Ga0.47As layer. The drain is a n+ In0.53Ga0.47As (Si doping of 1 × 1018 /cm3).
In this study, a wet etching method was applied to fabricate TFETs by exposing the InGaAs channel layer. Different materials were studied for insulators including SiO2 by PECVD and Al2O3/HfO2 by ALD. The n-TFET with best current and S.S. performance is a device with drain length of 2 μm and insulator of Al2O3/HfO2 (EOT of 2 nm). The characteristics of this device demonstrated the best S.S. of 240 mV/dec, on/off current ratio of 1.52 × 104 and maximum ON current of 9.33 μA/μm .
|| Committee, I.R., "International Technology Roadmap for Semiconductors, " 2011 Edition. Semiconductor Industry Association.|
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