自組式鍺奈米球/二氧化矽/矽鍺合金閘堆疊異質結構之介面工程最佳化探討

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：10

、訪客IP：18.220.13.70

姓名

楊國慶(Kuo-ching Yang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

自組式鍺奈米球/二氧化矽/矽鍺合金閘堆疊異質結構之介面工程最佳化探討
(Optimization on self-organized Ge-nanoball/SiO2/SiGe gate-stacking heterostructure with interface engineering)

相關論文

★ 高效能矽鍺互補型電晶體之研製	★ 高速低功率P型矽鍺金氧半電晶體之研究
★ 應變型矽鍺通道金氧半電晶體之研製	★ 金屬矽化物薄膜與矽/矽鍺界面反應之研究
★ 矽鍺異質源/汲極結構與pn二極體之研製	★ 矽鍺/矽異質接面動態啓始電壓金氧半電晶體之研製
★ 應用於單電子電晶體之矽/鍺量子點研製	★ 矽鍺/矽異質接面動態臨界電壓電晶體及矽鍺源/汲極結構之研製
★ 選擇性氧化複晶矽鍺形成鍺量子點的光特性與光二極體研製	★ 選擇性氧化複晶矽鍺形成鍺量子點及其在金氧半浮點電容之應用
★ 鍺量子點共振穿隧二極體與電晶體之關鍵製程模組開發與元件特性	★ 自對準矽奈米線金氧半場效電晶體之研製
★ 鍺浮點記憶體之研製	★ 利用選擇性氧化單晶矽鍺形成鍺量子點之物性及電性分析
★ 具有自我對準電極鍺量子點單電洞電晶體之製作與物理特性研究	★ 具有自我對準下閘電極鍺量子點單電洞電晶體之研製

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

本論文利用選擇性氧化複晶矽鍺柱/氮化矽/矽基材的結構來形成一體成型鍺奈米球/二氧化矽/矽鍺合金之金氧半異質結構。在透過元件結構的實驗設計，包含利用提升鍺奈米球的直徑大小來增加鍺奈米球的電容，以及將非鍺奈米球區域製作區域性的溝渠隔離區來降低寄生效應。成功地將鍺奈米球所貢獻的電容與周圍寄生電容的比例提升至約1比1左右，以利於提升鍺奈米球區域之介面缺陷密度萃取的準確性以評估探討介面特性。此外，本文同時製作“鋁/二氧化矽/鍺奈米球”以及“鍺化鎳/二氧化矽/矽鍺合金”之兩種金氧半電容結構，分別探討“二氧化矽/鍺奈米球”以及“二氧化矽/矽鍺合金”之間的介面品質。
透過變溫高低頻之電容-電壓量測分析，所萃取出二氧化矽/鍺奈米球之間的介面缺陷密度約3-4×1011 cm-2eV-1，二氧化矽/矽鍺合金之間的介面缺陷密度約3.5-5.5×1011 cm-2eV-1。兩者皆證明鍺/二氧化矽/矽鍺合金的介面之異質結構具有元件等級的介面品質。此外，本文透過調變鍺奈米球的大小與鑽入矽基板的深度來得以有效地控制矽鍺殼的長度與厚度，再搭配鍺奈米球介面的應力工程，有利於日後鍺通道金氧半電晶體的製作。

摘要(英)

In this thesis, we demonstrated a unique approach to generate a self-organized Ge-nanoball/SiO2/SiGe heterostructure on the Si substrate through the selective oxidation of poly-Si0.83Ge0.17 nano-pillar over buffer layers of Si3N4 that were deposited over the Si substrates. In order to investigate the interface properties of this designer heterostructure, experimental designs of device structures, including increasing the diameter of Ge-nanoball to enhance the capacitance of Ge and making trench isolation to reduce the parasitic effect are employed. We are able to further increase the ratio of the capacitance contributed by Ge-nanoball to that by the surrounding parasitic capacitance to about 1：1, leading to more accurate extraction of interface trap density within Ge-nanoball region. Accordingly, we fabricate Al/SiO2/Ge-nanoball and NiGe/SiO2/SiGe metal oxide semiconductor capacitors to explore the interface quality properties between SiO2 and Ge-nanoball as well as between SiO2 and SiGe shell, respectively.
The extracted interface trap density (Dit) from temperature-dependent high- and low-frequency capacitance-voltage (C-V) characteristics was about 3-4×1011 cm-2eV-1 between SiO2 and Ge-nanoball, and about 3.5-5.5×1011 cm-2eV-1 between SiO2 and SiGe. These results indicate superior interfacial properties in the studied Ge-nanoball/SiO2/SiGe on Si heterostructure, which is a promising candidate for high-performance Ge MOSFETs.

關鍵字(中)

★ 鍺金氧半電容
★ 鍺奈米球
★ 介面工程
★ 介面缺陷密度

關鍵字(英)

★ Ge MOS Capacitor
★ Ge-nanoball
★ interface engineering
★ interface trap density

論文目次

目錄
中文摘要.....................................................................................................................................I
英文摘要....................................................................................................................................II
致謝......................................................................................................................................IV
目錄......................................................................................................................................VI
圖目錄....................................................................................................................................VIII
表目錄.....................................................................................................................................XII
第一章簡介.............................................................................................................................1
1-1 前言.............................................................................................................................1
1-2 鍺材料的元件與製程挑戰.........................................................................................3
1-3 製作一體成型鍺奈米球/二氧化矽/矽鍺合金異質結構的回顧與利基..................5
1-4 研究動機....................................................................................................................6
1-5 論文的整體架構........................................................................................................6
第二章鍺奈米球金氧半電容元件最佳化研究之模組開發..............................................13
2-1 前言...........................................................................................................................13
2-2 降低寄生電容...........................................................................................................13
2-2-1 提升鍺奈米球所佔面積的比例..................................................................14
2-2-2 減少非主動區的寄生電容..........................................................................15
2-3 鍺基板之標準清洗流程...........................................................................................17
2-4 利用自我對準之金屬鍺化鎳的製作與探討...........................................................18
第三章鍺奈米球電容元件的製作.......................................................................................29
3-1 前言...........................................................................................................................29
3-2 鍺奈米球電容元件的製作流程...............................................................................30
第四章鍺奈米球電容元件的量測與分析...........................................................................38
4-1 前言...........................................................................................................................38
4-2 常見的計算介面缺陷密度之方法介紹...................................................................38
4-3 變溫高低頻電容-電壓特性來萃取介面缺陷密度在能隙分佈的原理.................43
4-4 鍺奈米球電容元件的量測結果與分析討論...........................................................45
4-3-1 鋁/二氧化矽/鍺奈米球結構之電容特性分析...........................................45
4-3-2 鍺化鎳/二氧化矽/矽鍺合金結構之電容特性分析...................................47
第五章總結與未來展望.......................................................................................................62
參考文獻...................................................................................................................................64

參考文獻

參考文獻
[1] D. Kuzum, “Interface-engineered Ge MOSFETs for future high performance CMOS applications,” dissertation for the degree of doctor, Stanford university (2009).
[2] M. Lundstrom, “Elementary scattering theory of the Si MOSFET,” IEEE Electron Device Lett., 18, 361 (1997).
[3] Y. Oshima, M. Shandalov, Y. Sun, P. Pianetta, and P. C. McIntyre, “Hafnium oxide/germanium oxynitride gate stacks on germanium: Capacitance scaling and interface state density,” Appl. Phys. Lett., 94, 183102 (2009).
[4] Q. Xie, J. Musschoot, M. Schaekers, M. Caymax, A. Delabie, X. P. Qu, Y. L. Jiang, S. VandenBerghe, J. Liu, and C. Detavernier, “Ultrathin GeOxNy interlayer formed by in situ NH3 plasma pretreatment for passivation of germanium metal-oxide-semiconductor devices,” Appl. Phys. Lett., 97, 222902 (2010).
[5] N. Wu, Q. Zhang, C. Zhu, D. S. H. Chan, A. Du, N. Balasubramanian, M. F. Li, A. Chin, J. K. O. Sin and D. L. Kwong, “A TaN-HfO2 Ge pMOSFET with Novel SiH4 surface passivation,” IEEE Electron Device Lett., 25, 631 (2004).
[6] J. Mitard, B. De Jaeger, F. E. Leys, G. Hellings, K. Martens, G. Eneman, D. P. Brunco, R. Loo, J. C. Lin, D. Shamiryan, T. Vandeweyer, G. Winderickx, E. Vrancken, C. H. Yu, K. De Meyer, M. Caymax, L. Pantisano, M. Meuris, M. Heyns, and M. Mitard, “Record ION/IOFF performance for 65 nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability,” Tech. Dig. Int. Electron Devices Meets., 873 (2008).
[7] D. Kuzum, T. Krishnamohan, A. J. Pethe, A. K. Okyay, Y. Oshima, Y. Sun, J. P. Mc Vittie, P. A. Pianetta, P. C. McIntyre, and K. C. Saraswat, “Ge-interface engineering with ozone oxidation for low interface-state density,” IEEE Electron Device Lett., 29, 328 (2008).
[8] H. Matsubara, T. Sasada, M. Takenaka, and S. Takagi, “Evidence of low interface trap density in GeO2/Ge metal-oxide-semiconductor structures fabricated by thermal oxidation,” Appl. Phys. Lett., 93, 032104 (2008).
[9] K. C. Saraswat, C. O. Chui, D. Kim, T. Krishnamohan, and A. Pethe, “High mobility materials and novel device structures for high performance nanoscale MOSFETs,” Tech. Dig. Int. Electron Devices Meets., 1 (2006).
[10] A. Satta, E. Simoen, T. Clarysse, T. Janssens, A. Benedetti, B. De Jaeger, M. Meuris, and W. Vandervorst, “Diffusion, activation, and recrystallization of boron implanted in preamorphized and crystalline germanium,” Appl. Phys. Lett., 87, 172109 (2005).
[11] P. Zimmerman, G. Nicholas, B. De Jaeger, B. Kaczer, A. Stesmans, L. A. Ragnarsson, D. P. Brunco, F. E. Leys, M. Caymax, G. Winderickx, K. Opsomer, M. Meuris, and M. M. Heyns, “High performance Ge pMOS devices using a Si-compatible process flow,” Tech. Dig. Int. Electron Devices Meets., 655 (2006).
[12] Y. Nakakita, R. Nakane, T. Sasada, H. Matsubara, M. Takenaka, and S. Takagi, “Interface-controlled self-align source/drain Ge pMOSFETs using thermally-oxidized GeO2 interfacial layers,” Tech. Dig. Int. Electron Devices Meets., 877 (2008).
[13] A. Satta, T. Janssens, T. Clarysse, E. Simoen, M. Meuris, A. Benedetti, I. Hoflijk, B. De Jaeger, C. Demeurisse, and W. Vandervorst, “P implantation doping of Ge: Diffusion, activation, and recrystallization,” J. Vac. Sci. Technol. B, 24, 494 (2006).
[14] C. O. Chui, L. Kulig, J. Moran, W. Tsai and K. C. Saraswat, “Germanium n-type shallow junction activation dependences,” Appl. Phys. Lett., 87, 091909 (2005).
[15] P. Tsipas, and A. Dimoulas, “Modeling of negatively charged states at the Ge surface and interfaces,” Appl. Phys. Lett., 94, 012114 (2009).
[16] A. Dimoulas, P. Tsipas, A. Sotiropoulos, and E. K. Evangelou, “Fermi-level pinning and charge neutrality level in germanium,” Appl. Phys. Lett., 89, 252110 (2006).
[17] 張宇瑞，“鍺量子點在氮化矽中的形成機制與鍺量子點可見光光二極體的研製”，碩士論文，國立中央大學，民國100年。
[18] C. C. Wang, P. H. Liao, M. H. Kuo, T. George, and P. W. Li, “The curious case of exploding quantum dots: anomalous migration and growth behaviors of Ge under Si oxidation,” Nanoscale Res. Lett., 8, 192 (2013).
[19] 許庭嘉，“一體成型鍺量子點/二氧化矽/矽異質結構之形成與其介面工程探討”，碩士論文，國立中央大學，民國102年。
[20] M. H. Kuo, C. C. Wang, W. T. Lai, T. George, and P. W. Li, “Designer Ge quantum dots on Si: A heterostructure configuration with enhanced optoelectronic performance,” Appl. Phys. Lett., 101, 223107 (2012).
[21] P. H. Liao, T. C. Hsu, K. H. Chen, T. H. Cheng, T. M. Hsu, C. C. Wang, T. George, and P. W. Li, “Size-tunable strain engineering in Ge nanocrystals embedded within SiO2 and Si3N4,” Appl. Phys. Lett., 105, 172106 (2014).
[22] D. P. Bruno, B. De Jaeger, G. Eneman, J. Mitard, G. Hellings, A. Satta, V. Terzieva, L. Souriau, F. E. Leys, G. Pourtois, M. Houssa, G. Winderickx, E. Vrancken, S. Sioncke, K. Opsomer, G. Nicholas, M. Caymax, A. Stesmans, J. Van Steenbergen, P. W. Mertens, M. Meuris, and M. M. Heyns, “Germanium MOSFET Devices: Advances in Materials Understanding, Process Development, and Electrical Performance,” J. Electrochem. Soc., 155, H552 (2008).
[23] S. Gaudet, C. Detavernier, A. J. Kellock, P. Desjardins, and C. Lavoie, “Thin film reaction of transition metals with germanium,” J. Vac. Sci. Technol. A, 24, 474 (2006).
[24] V. Carron, M. Ribeiro, P. Besson, G. Rolland, J. M. Hartmann, V. Loup, S. Minoret, L. Clavelier, C. Leoyer, and T. Billon, “Nickel selective etching studies for self-aligned silicide process in Ge and SiGe based devices,” ECS Trans., 3, 643 (2006).
[25] V. Carron, P. Besson, F. Pierre, “Wet Etching step evolution for selective removal on silicide or germanide applications,” ECS Trans., 11, 309 (2007).
[26] B. D. Jaeger, B. Kaczer, P. Zimmerman, K. Opsomer, G. Winderickx, J. Van Steenbergen, E. Van Moorhem, V. Terzieva, R. Bonzom, F. Leys, C. Arena, M. Bauer, C. Werkhoven, M. Caymax, M. Meuris and M. Heyns, “Ge deep sub-micron HiK/MG pFETs with superior drive compared to Si HiK/MG state-of-the-art reference,” Semicond. Sci. Technol., 22, S221 (2007).
[27] M. Tang, W. Huang, C. Li, H. Lai, and S. Chen, “Thermal stability of nickel germanide formed on tensile-strained Ge epilayer on Si substrate,” IEEE Electron Device Lett., 31, 863 (2010).
[28] C. Demeurisse, K. Opsomer, “Method for forming a self-aligned germanide and devices obtained thereof,” U. S. Patent, 20050196962 (2005).
[29] D. K. Schroder, Semiconductor Material and Device Characterization: Wiley (2006).
[30] C. N. Berglund, “Surface states at steam-grown silicon-silicon dioxide interfaces”, IEEE Trans. Electron Devices, 13, 701 (1966).
[31] L. M. Terman, “An investigation of surface states at a Silicon/Silicon Oxide interface employing metal-oxide-silicon diodes,” Solid-State Electron. 5, 285 (1962).
[32] R. Castagné, and A. Vapaille, “Description of SiO2-Si interface properties by means very low frequency MOS capacitance measurements,” Surf. Sci. 28, 157 (1971).
[33] K. Martens, C. O. Chui, G. Brammertz, B. De Jaeger, D. Kuzum, M. Meuris, M. M. Heyns, T. Krishnamohan, K. Saraswat, H. E. Maes, and G. Groeseneken, “On the correct extraction of interface trap density of MOS devices with high-mobility semiconductor substrates,” IEEE Trans. Electron Devices, 55, 547 (2008).
[34] J. S. Brugler, and P. G. A. Jespers, “Charge pumping in MOS devices,” IEEE Trans. Electron Devices, 16, 297 (1969).
[35] E. H. Nicollian, and J. R. Brews, MOS Physics and Technology: Wiley (2003).
[36] D. K. Nayak, K. Kamjoo, J. S. Park, J. C. S. Woo and K. Wang, “Rapid isothermal processing of strained GeSi layers,” IEEE Trans. Electron Devices, 39, 56 (1992).

指導教授

李佩雯(Pei-wen Li)

審核日期

2015-1-21

推文