應用於 K 頻段射頻接收機之寬頻低功耗 CMOS 低雜訊放大器之研製

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姓名

簡菁儀(Ching-I Chien) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於 K 頻段射頻接收機之寬頻低功耗 CMOS 低雜訊放大器之研製
(Implementation on Wideband Low Power CMOS Low Noise Amplifier for K-Band RF Receiver Front-end)

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摘要(中)

本論文主要在探討K頻段寬頻、低雜訊之低雜訊放大器設計方法，文中提出了三個實現寬頻、低功耗特性的電路設計。電路採用tsmc 0.18-μm CMOS及tsmc 90-nm CMOS兩種製程。
第一個電路設計為一個三級共源極串聯之寬頻低功耗低雜訊放大器，欲設計ㄧ個寬頻之低雜訊放大器，本電路將三級電晶體增益分別匹配在不同的中心頻率下，預期其整體頻寬能到寬頻設計，由於此電路操作於高頻頻率，電晶體內部寄生效應轉趨明顯，因此電路中使用多個共振電路消除寄生效應，進而達到提升增益、降低雜訊之效果；本電路使用tsmc 0.18-μm CMOS製程設計，電路量測結果在24.3 GHz有最大增益7.78 dB，其3-dB頻寬從18 - 28.6 GHz （共10.6 GHz），量測最小雜訊為5.3 dB，線性度量測結果P1dB為-10 dBm、IIP3為-1 dBm，總功率消耗為7.07 mW，實際晶片大小（含下針測試pads）為0.89 × 0.83 mm2。
第二個低雜訊放大器電路為共源極串聯疊接架構，此電路設計重點為將第二級電路使用疊接架構，優點在於疊接架構可提供比共源極電路更大的增益，且由於電路架構關係，增加電路之隔離度，由於高頻電容寄生效應會造成雜訊增加，因此在疊接架構兩顆電晶體間串連一電感來降低雜訊。此電路量測最大增益為8.6 dB，其3-dB頻寬從19.4 - 27.8 GHz（共8.4 GHz），量測最小雜訊為6.8 dB。線性度量測結果P1dB為-10.5 dBm、IIP3為1.5 dB，總消耗功率為10.5 mW，晶片大小為0.89 × 0.83 mm2。
最後一個電路為使用tsmc 90-nm CMOS製程設計之變壓器回授既電流再生之寬頻低功耗低雜訊放大器，本次電路為單級疊接架構，將輸入匹配使用一變壓器回授，其優點在於可提升電路增益，為了使得電路操作在低功耗條件下，將電流再生技術加入疊接架構中，達到提高增益、降低功耗之效果。此電路量測結果在23 GHz有11.4 dB的增益，其3-dB頻寬從17.2 - 30 GHz（共12.8 GHz），量測雜訊最小為3.65 dB，而在頻寬內雜訊變化為3.65 - 4.18 dB。線性度量測結果P1dB為-17.5 dBm、IIP3為-6.1 dBm，電路總消耗功率為6.11 mW，晶片面積為0.95 × 0.6 mm2。

摘要(英)

The primary target of this thesis is to design wideband and low power K-band low noise amplifier (LNA). There are three different circuit designs which are design in tsmc 0.18-μm CMOS and tsmc 90-nm CMOS processes.
The first LNA circuit is a wideband, low power LNA using three stages common-source topology. In order to obtain a wideband response, the stagger tuning technique is utilized. At high frequencies, since the parasitic capacitances degrade the gain and contribute considerable noise, series-peaking inductors are used to resonate the parasitic capacitances. The proposed LNA achieved a measured maximum gain of 7.78 dB at 24.3 GHz. The 3-dB bandwidth is 10.6 GHz from 18 - 28.6 GHz. The minimum noise figure is 5.3 dB. The input 1-dB gain compression point (P1dB) is -10 dBm, and the third-order intercept point (IIP3) is -1 dBm. Total power consumption is 7.07 mW, and the chip size including testing pads is 0.89 × 0.83 mm2.
The second circuit is a two-stage wideband low noise amplifier. The first stage of the LNA adopted common-source topology with inductive source-degeneration to achieve both impedance and noise matching simultaneously. Meanwhile, the second stage used cascode topology. This topology can mitigate the Miller effects and improves the isolation between input/output ports. However, at high frequency, the parasitic capacitances in cascode topology also degrade the gain and contribute considerable noise. Accordingly, a series inductor is utilized to resonate the effect of the parasitic capacitance. Based on this design consideration, the LNA shows a gain of 8.6 dB with 10.5 mW power consumption, and a minimum noise figure of 6.8 dB. The P1dB is -10.5 dBm, and the IIP3 is 1.5 dBm. Total chip size including pads is 0.89 × 0.83 mm2.
The final LNA circuit is a wideband, low power low noise amplifier with transformer feedback input matching and the current-reused topology in 90-nm CMOS process. The current-reused technique is employed to reduce the power consumption. The input matching adopts a gate-source feedback transformer to achieve impedance and noise matching. The proposed LNA achieves a gain of 11.4 dB over a 3-dB bandwidth from 17 to 30 GHz and a minimum noise figure of 3.65 dB. The measured P1dB is -17.5 dBm and the IIP3 is -6.1 dBm at 24 GHz. The LNA consume only 6.11 mW from a 1.3-V supply. The chip size is 0.95 × 0.6 mm2.

關鍵字(中)

★ 低雜訊放大器
★ K頻段
★ 寬頻
★ 低功耗

關鍵字(英)

★ low noise amplifier
★ K-band
★ wideband
★ low power

論文目次

摘要 i
Abstract iii
誌謝 v
目錄 vii
圖目錄 ix
表目錄 xi
第一章緒論 1
1-1 研究動機 1
1-2 K頻段發展與研究現況 2
1-3 章節介紹 4
第二章低雜訊放大器 5
2-1 低雜訊放大器介紹 5
2-2 低雜訊放大器重要參數 6
2-2-1 S參數(S-Parameters) 6
2-2-2 雜訊指數 6
2-2-3 穩定度 7
2-2-4 功率消耗 7
2-2-5 線性度 8
2-3 雜訊探討 9
2-3-1 雜訊種類 9
2-3-2 雜訊電路分析與計算 12
2-3-3 低雜訊放大器架構簡介 14
第三章使用0.18-μm CMOS 設計之低雜訊放大器 15
3-1 三級共源極串聯之低電路架構 15
3-1-1 電路模擬與量測結果 22
3-1-2 結果與討論 31
3-2 共源極串聯疊接架構之低雜訊放大器 34
3-2-1 電路架構 34
3-2-2 電路模擬與量測結果 38
3-2-3 結果與討論 44
第四章使用90−nm CMOS設計之低雜訊放大器 48
4-1 電路架構 48
4-1-1 變壓器回授電路分析 50
4-2 電路模擬與量測結果 56
4-3 結果與討論 61
第五章結論 63
5-1 結論 63
5-2 未來方向 64
參考文獻 65

參考文獻

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指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2014-7-7

推文