博碩士論文 101521037 詳細資訊




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姓名 李孟翰(Meng-han Li)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 多相位微波及毫米波低相位雜訊 時脈產生器之研製
(Multi-phase Microwave and Millimeter-wave Low Phase Noise Clock Generators)
相關論文
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★ 微波與毫米波寬頻主動式降頻器★ 微波及毫米波注入式除頻器與振盪器暨射頻前端應用
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摘要(中) 本論文主要是針對多相位微波及毫米波低相位雜訊訊號源積體電路的研製。首先,使用台積電0.18 μm互補式金屬氧化物半導體製程實現一個應用在2.5 GHz的多相位時脈產生器,藉由壓控延遲迴路及相位補償電路,使得輸出的相位誤差可以進一步改善。八相位時脈產生器操作頻寬為1.8 ~ 3 GHz,當輸入信號為2.5 GHz時,其輸出的最大相位誤差為2.67°,且在偏移中心頻1 kHz~40 MHz的範圍內此電路最高累計之抖動量約為627.2 fs,電路直流消耗為39.6 mW,晶片面積為0.65×0.65 mm2。
第三章提出一個應用於W頻段的高功率疊接差動壓控振盪器(VCO),使用台積電90 nm 互補式金屬氧化物半導體製程設計和實現。為了確保疊接壓控振盪器為差動輸出
,因此可將壓控振盪器拆成等效奇模態電路和偶模態電路,在奇模態下電路必須滿足振盪條件,而偶模態電路則不會。量測輸出功率和直流轉換效率分別達到3.3 dBm和2.8%,振盪頻率可從93.6到98.7 GHz。並且使用了Q值增強架構來降低相位雜訊,相位雜訊在1 MHz頻率偏移時為-101.1 dBc/Hz,晶片面積為0.45×0.45 mm2。進一步利用此W頻段差動振盪器延生設計一個W頻段四相位振盪器,經由四個反射式的調變器將四個輸出相位整合成一個輸出,以便於W頻段四相位輸出的量測,並且對其有詳細的分析討論及模擬結果。此W頻段四相位振盪器,模擬的相位雜訊在1 MHz頻率偏移時為-93 dBc/Hz,而相位誤差與振幅誤差分別為2.37°與0.048 dB。
第四章使用延遲鎖定迴路自我對準注入的技術,實現兩個次諧波(N=16)注入鎖定鎖相迴路次諧波數(N)分別為8與16。為了進一步增加次諧波注入振盪器的鎖定頻寬,設計一個N=8的次諧波注入鎖定鎖相迴路,其模擬鎖定頻寬為59 MHz,模擬相位偵測器及迴路濾波器,最高操作頻率為312.5 MHz。N=16次諧波注入鎖定鎖相迴路量測結果在操作頻率為2.4 GHz及偏移中心頻為1 MHz時,量測相位雜訊為-124.9 dBc/Hz ,均方根值(rms)抖動為193.2 fs。最後,在第五章總結此篇論文的研究成果。
摘要(英) Design and analysis of multi-phase low phase noise microwave and millimeter-wave signal source intergrated circuits is presented in this thesis. A 2.5-GHz Multi-phase clock generator using a 0.18-μm CMOS process is presented in chapter 2. By utilizing a delay-locked loop (DLL) and a phase interpolator (PI), the phase accuracy of the multi-phase clock generator can be further enhanced. The bandwidth of the multi-phase clock generator is from 1.8 GHz to 3 GHz. The measured maximum phase error is 2.67°and the measured rms jitter intergrted from 1kHz to 40 MHz is 627.2 fs when the operating frequency is 2.5 GHz. The total dc power consumption is 39.6 mW. The chip size is 0.65×0.65 mm2.
A W-band high output power differential cascode voltage-controlled oscillator (VCO) using TSMC 90 nm CMOS process is presented in Chapter 3. To ensure the differential operation for the cascode VCO, the even- and odd-mode analysis is adopted in the circuit design. The proposed VCO exhibits a maximum output power of 3.3 dBm, and a maximum efficiency of 2.8 %. The measured tuning range is from 93.6 to 98.7 GHz. Also, the Q-enhancement technique is introduced to reduce the phase noise. The measured phase noise is -101.1 dBc/Hz at 1-MHz offset. The chip size is 0.45×0.45 mm2. Based on the differential cascode VCO topology, an innovative quadrature cascode VCO is proposed . The simulated phase noise is -93 dBc/Hz at 1-MHz offset and the simulated phase error and amplitude error are 2.37° and 0.048 dB.
A 2.5-GHz Subharmonically Injection-locked PLL with DLL self-aligned injection using 0.18-μm CMOS technology is presented in Chapter 4. To further increase the locking rang of sub-harmonically injection-locked VCO, two SILPLLs with sub-harmonically numbers(N) of 8 and 16 is proposed. The simulated locking range of SILVCO with N=8 is 59 MHz, and Phase Frequency Detector and loop filter are also presimulated with reference frequency of up to 312.5 GHz. As the operation frequency is 2.4 GHz, the measured phase noise of the proposed SILPLL with N=16 is -124.9 dBc/Hz at 1 MHz offset with a rms jitter of 193.2 fs. Finally, we summarize the conclusion in Chapter 5.
關鍵字(中) ★ 多相位時脈產生器
★ 微波及毫米波時脈產生器
★ 低相位雜訊時脈產生器
關鍵字(英) ★ Multi-phase Clock Generators
★ Microwave and Millimeter-wave Clock Generators
★ Low Phase Noise Clock Generators
論文目次 摘要 VI
ABSTRACT VII
誌謝 IX
目錄 X
圖目錄 XIII
表目錄 XX
第一章 緒論 1
1.1 研究動機與背景 1
1.2 研究發展及現況 1
1.3 貢獻 3
1.4 論文架構 4
第二章 2.5 GHZ多相位時脈產生器 6
2.1 簡介 6
2.2 多相位時脈產生器架構整理 7
2.3 延遲鎖定迴路架構介紹 8
2.4 延遲鎖定迴路理論分析 9
2.4.1 迴路穩定度分析[13]-[14] 9
2.4.2 迴路相位雜訊抖動分析 14
2.5 電路設計與分析 19
2.5.1 延遲鎖定迴路 19
2.5.2 壓控延遲單元 20
2.5.3 相位補償電路 22
2.5.4 全電路系統模擬結果 24
2.6 量測結果與討論 26
2.7 結論 32
第三章 W頻段高功率多相位壓控振盪器 33
3.1 簡介 33
3.2 電路架構設計與分析 34
3.2.1 Q值增強架構簡介 35
3.2.2 電路小訊號模型轉移函數與等效Q值推導 37
3.2.3 W頻段差動壓控振盪器電路簡介 44
3.2.4 迴授網路分析 46
3.3 電路實現與量測結果討論 53
3.4 結論 60
3.5 W頻段四相位高功率壓控振盪器 62
3.5.1 四相位壓控振盪器簡介 62
3.5.2 W頻段四相位高功率壓控振盪器架構介紹 65
3.5.3 反射式調變器設計[43]-[44] 69
3.5.4 交互耦合路徑設計 73
3.5.5 W頻段四相位高功率壓控振盪器佈局與模擬結果 75
3.5.6 W頻段四相位高功率壓控振盪器量測考量 79
第四章 2.5 GHZ具自我校正功能之注入鎖定鎖相迴路 82
4.1 鎖相迴路簡介 82
4.1.1 簡介 82
4.1.2 鎖相迴路基本架構 82
電壓控制振盪器 82
除頻器Frequency Divider 83
相位頻率偵測器Phase Frequency Detector/Phase Detector & Charge Pump 85
迴路濾波器與迴路分析 85
4.1.3 次諧波注入鎖相迴路簡介 89
4.2 電路架構設計與分析 (N=16) 92
4.2.1 次諧波注入鎖定振盪器 93
4.2.2 壓控延遲線 94
4.2.3 TSPC除頻器 95
4.2.4 相位頻率偵測器 96
4.2.5 脈衝時脈產生器 98
4.2.6 SILPLL系統模擬結果 98
4.3 2.5 GHZ SILPLL 除八(N=8)設計與分析 100
4.4 電路實現與量測結果討論 106
4.5 結論 113
第五章 結論 114
參考文獻 116
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指導教授 張鴻埜(Hong-Yeh Chang) 審核日期 2015-7-8
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