博碩士論文 101521085 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:21 、訪客IP:3.236.253.192
姓名 葉欲名(Yu-Ming Yeh)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 控制峰值溫度與電壓降之三維積體電路固定框架平面規劃
(Fixed-outline Floorplanning for Peak Temperature and IR-drop Controls in 3D ICs)
相關論文
★ 運算放大器之自動化設計流程及行為模型研究★ 高速序列傳輸之量測技術
★ 使用低增益寬頻率調整範圍壓控震盪器 之1.25-GHz八相位鎖相迴路★ 類神經網路應用於高階功率模型之研究
★ 使用SystemC語言建立IEEE 802.3 MAC 行為模組之研究★ 以回填法建立鎖相迴路之行為模型的研究
★ 高速傳輸連結網路的分析和模擬★ 一個以取樣方式提供可程式化邏輯陣列功能除錯所需之完全觀察度的方法
★ 抑制同步切換雜訊之高速傳輸器★ 以行為模型建立鎖相迴路之非理想現象的研究
★ 遞迴式類神經網路應用於序向電路之高階功率模型的研究★ 用於命題驗証方式的除錯協助技術之研究
★ Verilog-A語言的涵蓋率量測之研究★ 利用類神經模型來估計電源線的電流波形之研究
★ 5.2GHz CMOS射頻接收器前端電路設計★ 適用於OC-192收發機之頻率合成器和時脈與資料回復電路
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 由於積體電路的應用愈來愈廣泛使用在人類的生活中,因此積體電路的功能需求也愈來愈龐大,三維積體電路(3D ICs)便是在這股趨勢下產生。有別於一般所使用的二維積體電路(2D ICs),三維積體電路增加了垂直方向的連結,也因為三維積體電路是由多個二維積體電路堆疊而成,所以三維積體電路可以利用不同製程的二維積體電路製造,這便是三維積體電路異質整合的優勢。
三維積體電路雖然有許多優於二維積體電路的特性,但仍有許多待解決的問題。隨著供應電壓的降低與頻率的增加,峰值溫度(peak temperature)與峰值電壓降(peak IR-drop)的問題愈來愈明顯,加上在三維積體電路的結構中,有低熱導率(thermal conductivity)的材質在其中,因此三維積體電路的溫度問題更加嚴重。
本篇論文提出了一個流程,可以有效地控制三維積體電路的溫度與電壓降。我們在平面規劃(floorplanning)階段擺放電路區塊(blocks),並且考量固定框架(fixed-outline)的限制,讓我們在有限的空間做適當的使用。為了防止在擺置(placement)或繞線(routing)階段,電路區塊因為塞滿散熱型矽晶穿孔(thermal TSVs)而無法做繞線,我們提出的流程會提早考量訊號型矽晶穿孔(signal TSVs)的面積。
實驗結果可以得知提前在平面規劃階段考量熱與電壓降的問題,較在後平面規劃(post-floorplanning)階段才考量有效,但會犧牲部分線長(wirelength)來控制峰值溫度與電壓降。
摘要(英) As integrated circuits (ICs) are widely used in humans’ daily life, the number of functions of ICs is required to be more. Three dimensional ICs (3D ICs) are born with the trend. The difference between 3D ICs and traditional 2D ICs is that, 3D ICs are added the property of the vertical connection, which is made by through-silicon-vias (TSVs). 3D ICs have the feature of heterogeneous integration, which is that the dies with different manufacturing processes can be integrated to one IC.
Although 3D ICs have some powerful advantages comparing with 2D ICs, 3D ICs have two critical problems. One is heat issue, another is IR-drop. Due to the increasing number of circuit blocks and the effect of low thermal conductivity of 3D ICs, the heat is difficult to be dissipated. IR-drop issue is due to the increasing frequency and decreasing power supply voltage.
We propose a design flow in the floorplanning stage with fixed-outline constraints, which can control the peak temperature and the peak IR-drop of 3D ICs effectively. Besides, for considering routability, signal TSVs are added in advance to reserve area.
According to the experimental results, the proposed flow can control the peak temperature and the peak IR-drop under given constraints. Comparing with the previous work in the post-floorplanning stage, the proposed flow can reduce peak temperature about 40%. Although the total wirelength increases, the peak temperature and the peak IR-drop can be controlled effectively.
關鍵字(中) ★ 三維積體電路
★ 平面規劃
★ 散熱
★ 電壓降
★ 散熱型矽晶穿孔
★ 去耦合電容
關鍵字(英) ★ 3D ICs
★ floorplanning
★ thermal
★ ir-drop
★ thermal tsv
★ decoupling capacitors
論文目次 摘要 ......................................................................I
ABSTRACT ......................................................II
致謝 ......................................................................III
目錄 ......................................................................IV
圖目錄 ..............................................................VII
表目錄 ..............................................................IX
第一章、 三維積體電路 ......................................1
1-1 演進 ..............................................................1
1-2 關鍵技術 ......................................................3
1-2-1 矽晶穿孔技術 ..............................................4
1-2-2 堆疊技術 ......................................................5
1-3 挑戰 ..............................................................6
1-3-1 散熱議題 ......................................................7
1-3-2 電壓降議題 ..............................................8
1-4 論文結構 ....................................................10
第二章、 相關研究 ............................................11
2-1 考慮散熱議題與電壓降議題 ............................11
2-1-1 考慮散熱議題 ............................................11
2-1-2 考慮電壓降議題 ....................................12
2-1-3 同時考慮散熱與電壓降議題 ....................13
2-1-4 總結 ....................................................14
2-2 模擬方法 ....................................................15
2-2-1 溫度模擬 ....................................................15
2-2-2 電壓降模擬 ............................................17
第三章、 三維積體電路固定框架平面規劃 ............19
3-1 研究動機 ....................................................19
3-2 符號與名詞定義 ............................................20
3-3 問題描述 ....................................................21
3-4 流程圖 ....................................................23
3-4-1 輸入 ....................................................24
3-4-2 電路區塊擴大 ............................................24
3-4-3 合法化的平面規劃 ....................................25
3-4-4 電路區塊擴散 ............................................29
3-4-5 插入訊號型矽晶穿孔 ....................................30
3-4-6 快速模擬 ....................................................30
3-4-7 相鄰層峰值溫度是否重疊的判斷 ....................30
3-4-8 插入散熱型矽晶穿孔與去耦合電容 ............31
3-4-9 細部模擬 ....................................................33
3-4-10 峰值溫度與峰值電壓降是否達標的判斷 ....33
3-4-11 輸出 ....................................................33
第四章、 實驗設定與結果 ....................................34
4-1 實驗環境與參數設定 ....................................34
4-2 比較對象與實驗結果 ....................................35
4-2-1 比較對象 ....................................................35
4-2-2 實驗結果與討論 ....................................37
第五章、 結論 ....................................................41
第六章、 參考文獻 ............................................42
參考文獻 [1] M. Juergen Wolf, Peter Ramm, and Armin Klumpp, “Through Silicon Via Technology: R&D@ Fraunhofer IZM,” in Fraunhofer IZM, Tech. Rep, 2008
[2] International Technology Roadmap for Semiconductors, 2009
[3] M. Koyanagi, T. Fukushima, and T. Tanaka, “Three-Dimensional Integration Technology and Integrated Systems,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 409-415, 2009
[4] Jian-Qiang Lu, “3D Hyperintegration and Packing Technologies for Micro-Nano Systems,” in Proceedings of IEEE, pp. 18-30, 2009
[5] Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, and Chien-Nan Jimmy Liu, “ILP-based Inter-die Routing for 3D ICs,” in Proceedings of Asia and South Pacific Design Automation Conference, pp. 330-335, 2011
[6] Dae Hyun Kim, Krit Athikulwongse, and Sung Kyu Lim, “A Study of Through-silicon-via Impact on the 3D Stacked IC Layout,” in Proceedings of International Conference on Computer-Aided Design, pp. 674-680, 2009
[7] Yogiraj Pardhi, "Metallurgy - Advances in Materials and Processes," ISBN 978-953-51-0736-1, Published on September 2012
[8] Sungjun Im and K.Banerjee, "Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs," International Electron Devices Meeting, pp. 727-730, 2000
[9] Sachin S. Sapatnekar, "CAD for 3D circuits: Solutions and challenges," in VLSI/ULSI Multilevel Interconnection Conference, pp. 245-251, 2007
[10] Jason Cong and Yan Zhang, "Thermal Via Planning for 3D ICs," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 121-126, 2005
[11] Shiyou Zhao, Kaushik Roy, and Cheng-Kok Koh, "Decoupling Capacitance Allocation and Its Application to Power-Supply Noise-Aware Floorplanning,” in Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 1, pp. 81-92, 2002
[12] Jason Cong, Jie Wei, and Yan Zhang, "A Thermal-driven Floorplanning Algorithm for 3D ICs," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 306-313, 2004
[13] Yun Huang, Qiang Zhou, Yici Cai, and Haixia Yan, "A Thermal-driven Force-directed Floorplanning Algorithm for 3D ICs," in Proceedings of IEEE International Conference on Computer-Aided Design and Computer Graphics, pp. 497-502, 2009
[14] Linfu Xiao, Subarna Sinha, Jingyu Xu, and Evangeline F.Y. Young, "Fixed-outline Thermal-aware 3D Floorplanning," in Proceedings of Asia and South Pacific Design Automation Conference, pp. 561-567, 2010
[15] Eric Wong, Jacob Rajkumar Minz, and Sung Kyu Lim, "Decoupling Capacitor Planning and Sizing for Noise and Leakage Reduction," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 11, pp. 2023-2034, 2007
[16] Eric Wong, Jacob Minz, and Sung Kyu Lim, "Effective Thermal Via and Decoupling Capacitor Insertion for 3D System-On-Package", in Proceedings of Electronic Components and Technology Conference, pp. 1795-1801, 2006
[17] Yan-Wun Wang, Pao-Jen Huang, Tai-Chen Chen, and Chien-Nan Jimmy Liu, "Simultaneous Hotspot Temperature and Supply Noise Reductions using Thermal TSVs and Decoupling Capacitors," in Asia Symposium on Quality Electronic Design, pp. 245-248, 2013
[18] S. W. Ho, S. W. Yoon, Q. Zhou. K. Pasad, V. Kripesh, and J. H. Lau, "High RF Performance TSV Silicon Carrier for High Frequency Application," in Electronic Components and Technology Conference, pp. 1946-1952, 2008
[19] G. Katti, A. Mercha, M. Stucchi, Z. Tokei, D. Velenis, J. Van Olmen, C. Huyghebaert, A. Jourdain, M. Rakowski, I. Debusschere, P. Soussan, H. Oprins, W. Dehaene, K. De Meyer, Y. Travaly, E. Beyne, S. Biesemans, and B. Swinnen, "Temperature dependent electrical characteristics of Through-Si-Via (TSV) interconnections", in IEEE International Interconnect Technology Conference, pp. 1-3, 2010
[20] Jie Meng, Katsutoshi Kawakami, and Ayse K. Coskun, "Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints," in Proceedings of IEEE/ACM Design Automation Conference, pp. 648-655, 2012
[21] Wei Huang, Shougata Ghosh, Siva Velusamy, Karthik Sankaranarayanan, Kevin Skadron, and Mircea R. Stan, "Hotspot: A Compact Thermal Modeling Methodology for Early-stage VLSI Design," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 5, pp. 501-513, 2006
[22] Chris Chu and Yiu-Chung Wong, "FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 1, pp. 70-83, 2008
[23] Ming-Chao Tsai, Ting-Chi Wang, and Ting-Ting Hwang, "Through-silicon Via Planning in 3-D Floorplanning," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 8, pp. 1448-1457, 2011
[24] Paul Falkenstern, Yuan Xie, Yao-Wen Chang, and Yu Wang, "Three-dimensional Integrated Circuits (3D IC) Floorlpan and Power/Ground Network Co-synthesis," in Proceedings of Asia and South Pacific Design Automation Conference, pp. 169-174, 2010
[25] Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Li, and Yao-Wen Chang, "Efficient multi-layer obstacle-avoiding rectilinear steiner tree construction," in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 380-385, 2007
[26] Floorplan Benchmark [Online]. Available: http://vlsicad.eecs.umich.edu/BK/parquet/#BENCH
[27] Jinseong Choi, Madhavan Swaminathan, Nhon Do, and Raj Master, "Modeling of Power Supply Noise in Large Chips Using the Circuit-based Finite-difference Time-domain Method," in Transactions on Electromagnetic Compatibility, vol. 47, no. 3, pp. 424-439, 2005
指導教授 陳泰蓁、劉建男(Tai-Chen Chen Chien-Nan Jimmy Liu) 審核日期 2014-8-1
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明