博碩士論文 101521088 詳細資訊




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姓名 周芳瑜(Fang-Yu Jhou)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 考量功耗與阻抗之CMOS 電壓整流器自動化設計與佈局
(Automated CMOS Voltage Rectifier Design and Layout with Power and Impedance Consideration)
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摘要(中) 射頻電路的能量收集(energy harvesting)是近期相當熱門的研究,它可以將環
境中的能量轉換為電路所需的電源,使電路不需要額外的獨立電源即可運作。在
能量收集的電路中,整流器(rectifier)扮演著不可或缺的角色,因此,本論文針對狄克森多階整流器的架構,提出一套考量效率與輸入阻抗的自動化設計工具,可
自動依據使用者輸入的規格,找出符合規格的最佳電路設計,並自動產出相對應
的電路佈局。與之前的研究相比,本論文最大的特點在於將輸入阻抗納入考量,
讓使用者可以在效率與面積之間做一個適當的取捨,有效避免設計結束後阻抗匹
配電路不易設計的情況。
整套自動化工具包含了電路設計與電路佈局兩個部分,皆可在LINUX 上實
現,所產生的TCL 佈局批次命令檔,亦可在現有的EDA 工具順利執行,產出正
確無誤地佈局。從實驗數據的觀察可知,本論文所提出的工具確實可以在非常短
的時間內設計出符合使用者所給定規格之電路及其佈局,大大縮短了射頻電路上
繁瑣的設計流程。
摘要(英) For radio frequency (RF) circuits, energy harvesting is one of the hot research topics in recent years. By converting ambient energy into the required electrical energy, the circuit can still perform its functionality without any extra power source. In RF energy harvesting circuits, the most important part is the rectifier circuit. Therefore, this thesis proposes an automated design tool for CMOS multi-stage Dickson rectifiers to generate the required designs from specifications to layout with power and impedance considerations. In this thesis, impedance matching has been taken into consideration to have a proper trade off between area and performance.
Therefore, it can solve the difficulty in previous approaches to match the impedance after design.
The proposed automation tool is consisted of two parts, circuit sizing and IC layout, which have been implemented in LINUX already. The generated Tcl layout scripts have been tested in commercial EDA tools and generated the corresponding layout successfully. As demonstrated in the experimental results, this tool is able to
generate the required circuits and layouts that satisfy all users’ specifications in seconds. This is very helpful to shorten the complicated RF IC design flow.
關鍵字(中) ★ 電壓整流器
★ 自動化佈局
關鍵字(英)
論文目次 摘要................................................. i
Abstract ........................................... ii
致謝 ................................................ iii
目錄 ................................................ iv
圖目錄 .............................................. vii
表目錄 .............................................. ix
第一章、序論 ......................................... 1
1.1 研究動機 ........................................ 1
1.2 相關研究 ........................................ 3
1.3 論文結構 ........................................ 5
第二章、背景知識 ..................................... 6
2.1 整流器架構....................................... 6
2.1.1 倍壓器 ....................................... 6
2.1.2 Cockcroft-Walton Multiplier.................. 7
2.1.3 Dickson Voltage Multiplier .................. 8
2.1.4 Modified Dickson Voltage Multiplier ......... 9
2.2 阻抗匹配 ....................................... 10
2.2.1 匹配網路 ..................................... 10
2.2.2 L 型網路 ..................................... 11
2.2.3 螺旋電感(Spiral Inductor) .................... 15
2.3 Laker 之自動化佈局 .............................. 17
2.3.1 MOS 之自動化生成 .............................. 18
第三章、自動化設計流程 ................................ 20
3.1 設計流程 ....................................... 20
3.2 整流器參數計算................................... 21
3.2.1 計算最小級數.................................. 21
3.2.2 效率之計算.................................... 23
3.2.3 輸入阻抗求取.................................. 25
3.2.4 目標函數 .................................... 27
3.3 半區間法(Interval Halving)...................... 28
3.3.1 Region-elimination method .................. 28
3.3.2 Interval halving ............................ 30
3.4 電路模擬與抽取所需結果............................. 32
3.5 匹配網路計算.................................... 34
第四章、整流器之自動化生成 ............................ 35
4.1 NMOS ......................................... 35
4.2 Capacitor .................................... 36
4.3 整流器 ........................................ 37
第五章、實驗結果與分析 ............................... 39
5.1 實驗環境及佈局工具............................... 39
5.2 實驗結果 ...................................... 39
5.2.1 針對負載阻抗為100KΩ .......................... 40
5.2.2 針對負載阻抗為1MΩ ............................ 41
5.2.3 結果比較 .................................... 43
第六章、結論與未來展望 ............................... 45
參考文獻 .......................................... 46
參考文獻 [1] John F. Dickson, “On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique,” IEEE Solid-State Circuits, pp. 374-378, 1976.
[2] Sherlyn dela Cruz, Mark Gerard delos Reyes, Anastacia Alvarez, Maria Theresa de Leon, Christian Raymund Roque, “Design and implementation of passive RF-DC converters for RF power harvesting systems” IEEE TENCON, pp. 1503-1508, 2010.
[3] Toru Tanzawa, “An Optimum Design for Integrated Switched-Capacitor Dickson Charge Pump Multipliers With Area Power Balance”, IEEE Trans. on Power Electronics, pp. 534-538, 2014.
[4] Geoffroy Gosset and Denis Flandre, “Fully-Automated and Portable Design Methodologyfor Optimal Sizing of Energy-Efficient CMOSVoltage Rectifiers”, IEEE Trans. on Emerging and Selected Topics in Circuits and Systems, pp. 141-149, 2011.
[5] K. Kotani and T. Ito, “High Efficiency CMOS Rectifier Circuit with Self-Vth-Cancellation and Power Regulation Functions for UHFRFIDs”,ASSCC ’07. IEEE Asian, pp.119-122, 2007.
[6] Hao Gao, Peter Baltus, Reza Mahmoudi, Arthur van Roermund, “2.4GHz Energy Harvesting for Wireless Sensor Network”, IEEE Conf.on Wireless Sensors and Sensor Networks (WiSNet), pp.57-60, 2011
[7] J. Cockcroft and E. Walton, “Production of high velocity positive ions”,Proc. Royal Society of London, Series A, 1932.
[8] U. Karthaus and M. Fischer, “Fully integrated passive UHF RFID transponder IC with 16.7 μW minimum RF input power”, IEEE J. Solid-State Circui, pp. 1602-1608, 2003.
[9] Fei Yuan and Nima Soltani, “Design Techniques for Power Harvesting of Passive Wireless Microsensors”, IEEE Circuits and Systems, pp. 289-293,2008
[10] Fei Yuan, 2010 , “CMOS Circuits for Passive Wireless Microsystems”,New York, Springer.
[11] David M. Pozar, 2012, “Microwave_Engineering 4/ed”, United States,John Wiley.
[12] Heng-Ming Hsu, Member, IEEE, Kai-Yuen Chan, Hung-Chi Chien, and Han-Chien Kuan, “Analytical Design Algorithm of Planar Inductor Layout in CMOS Technology,” IEEE Trans. on Electron Devices, pp. 3208- 3213,2008.
[13] 鄭一民, “Designing Active Inductors by Multi-Stage RF CMOS Circuit”, 碩士論文, 逢甲大學, 2004.
[14] C.P. Yue and S.S Wong, “Physic modeling of spiral inductors on silicon,”IEEE Trans. on Electron Devices, pp. 560–568, 2000.
[15] LakerTM from Synopsys, http://www. synopsys.com
[16] 許家綾, “Designing Active Inductors by Multi-Stage RF CMOS Circuit”,碩士論文, 國立中央大學, 2011.
[17] Giuseppe Papotto, Francesco Carrara, Senior Member, “A 90-nm CMOS Threshold-Compensated RF Energy Harvester,” IEEE Journal of Solid-State Circuit, pp. 1985-1997, 2011.
[18] Kalyanmoy Deb, 2009, “Optimization for Engineering Design: Algorithms and Examples”, New Delhi, PHI Learning.
[19] Jun Yi, Student Member, IEEE, Wing-Hung Ki, Member, IEEE, and Chi-Ying Tsui, Member, IEEE, “Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications”,IEEE Trans. on Circuits and Systems I: Regular Papers, pp. 153-166,2007.
[20] Liu Dong-Sheng, Zou Xue-Cheng, Dai Kui, Li Si-Zheng, Hui Xue-Mei,Liu Yao, Tong Qiao-Ling, “New Design of RF Rectifier for Passive UHF
指導教授 劉建男(Chien-Nan Liu) 審核日期 2014-8-27
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