博碩士論文 101521103 詳細資訊




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姓名 陳宣豪(Shiuan-Hau Chen)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 應用於內容定址記憶體之具錯誤診斷能力自我修復方法
(Built-In Self-Repair Scheme with Fault Diagnosis Ability for Content Addressable Memories)
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摘要(中) 內容可定址記憶體 (content addressable memory, CAM) 在數位系統中扮演著重要的角色。為了支援平行搜尋的功能,一個CAM 單元 (cell) 是由一個儲存元件和一個比較元件所組成,這使得CAM在測試上比一個隨機存取記憶體(random access memory, RAM) 困難許多。由於愈來愈多的大容量CAM 被需要於網路相關的應用,有效的良率改善技術對於這些大容量嵌入式或獨立式CAM 是必要的。
內建自我修復 (built-in self-repair, BISR) 的技術是一個有效的方法,用來改善嵌入式CAM 的良率,而所使用之測試演算法的錯誤定位能力會是CAM自我修復的一個主要挑戰。為了觀察測試所回傳的結果,一個針對CAM的測試演算法中必須有比對的測試動作。然而,一旦比對動作偵測到一個錯誤,我們只能知道錯誤的行或列,錯誤單元的位置並不能得知。在本論文中,我們針對CAM提出了一個具有錯誤診斷能力的自我修復方法。其中,我們提出錯誤定位的演算法,用來找到錯誤單元的位置,使得具備優先權位址編碼器的CAM之修復效率能夠提升。此外,為了評估所提出之自我修復的修復效率,我們提出一個估算自我修復方法之修復率的評估工具。模擬結果顯示具錯誤診斷能力之自我修復的修復率要比不具備該能力之自我修復的修復率要好得多。在針對512x128 位元的CAM與使用TSMC 0.13um 製程的情況下,所提出的BISR 面積負擔約占3.29%。
摘要(英) Content addressable memory (CAM) plays an important role in many digital systems. For supporting the function of parallel search, a CAM cell is composed of a storage element and a comparator. This causes that the testing of CAM is more difficult than that of RAM. More and more large-capacity CAMs are needed for network-related applications. Effective yield-enhancement techniques are imperative for these large embedded or stand-alone CAMs.
Built-in self-repair (BISR) technique is one effective method for enhancing the yield of embedded memories. One main challenge of CAM BISR is that the fault location capability of the used test algorithms. A test algorithm for CAMs must have compare test operations for observing the test responses. Once a compare operation detects a fault, however, we only can know the faulty row/column and cannot know the location of faulty cell. In this thesis, we propose a BISR scheme with fault diagnosis capability for CAMs. A fault-location algorithm is proposed to identify the location of faulty cell in a CAM with priority address encoder. The BISR uses the fault-location algorithm to identify the location of faulty cells such that the repair efficiency is boosted. To evaluate the repair efficiency of the proposed BISR scheme, furthermore, an evaluation tool for estimating the repair rate of the BISR scheme is proposed. Simulation results show that the BISR with the fault diagnosis capability can
provide much better repair rate in comparison with the BISR without the fault diagnosis capability. The area overhead of the BISR circuit is about 3.29% for a 512x128-bit CAM using TSMC 0.13um CMOS standard cell library.
關鍵字(中) ★ 內容可定址記憶體
★ 內建自我修復
★ 修復率
關鍵字(英) ★ Content addressable memory
★ Built-in self-repair
★ Repair rate
論文目次 1 Introduction . . . . . . . . . . . . . . . . . . . . . 1
1.1 Content Addressable Memory . . . . . . . . . . . . . 1
1.1.1 Typical CAM Architecture . . . . . . . . . . . . . 1
1.1.2 Typical CAM Structures . . . . . . . . . . . . . . 3
1.2 CAM Test and Diagnosis . . . . . . . . . . . . . . . 4
1.2.1 Functional Faults of CAM . . . . . . . . . . . . . 4
1.2.2 Existing Test Algorithms for Comparison Faults . . 5
1.2.3 Fault Location Algorithm . . . . . . . . . . . . . 6
1.3 Existing Repair Schemes for CAM . . . . . . . . . . 7
2 Built-In Self-Repair of CAM . . . . . . . . . . . . . 9
2.1 Issues of Conventional CAM Repair . . . . . . . . . 9
2.2 Fault-Location Algorithm for CAMs with Priority Address Encoder . . . . . . . . . . . . . . . . . . . . 11
2.2.1 Fault-Location Algorithm for Faulty Column . . . 11
2.2.2 Fault-Location Algorithm for Faulty Row . . . . . 15
2.3 Proposed BISR for CAMs . . . . . . . . . . . . . . 19
2.3.1 BIST Architecture with fault-location capability. 19
2.3.2 BIRA Architecture . . . . . . . . . . . . . . . . 23
2.4 Analysis and Simulation Result . . . . . . . . . . 28
3 Evaluation of Repair Efficiency for CAMs . . . . . . 33
3.1 Repair Rate Simulator for CAMs . . . . . . . . . . 33
3.1.1 Defect Injection and Fault Translation . . . . . 34
3.1.2 Test Algorithm Simulation . . . . . . . . . . . . 36
3.1.3 Addition of Repeated Detection . . . . . . . . . 39
3.1.4 Redundancy Analysis . . . . . . . . . . . . . . . 43
3.1.5 Repair Rate Evaluation and Static . . . . . . . . 46
3.2 Simulation Result and Discussion . . . . . . . . . 48
3.2.1 Adjusted Specification File . . . . . . . . . . . 48
3.2.2 CAM Repair Rate with Diagnosis . . . . . . . . . 51
3.2.3 CAM Repair Rate with Disablement . . . . . . . . 53
3.2.4 CAM Repair Rate with Mixed Strategies . . . . . . 53
4 Conclusion . . . . . . .. . . . . . . . . . . . . . . 57
參考文獻 [1] K.-J. Lin and C.-W. Wu, “Testing content-addressable memories using functional fault models and march-like algorithms,” in IEEE Trans. on Computer-Aided Design of IntegratedCircuits and Systems, no. 5, May 2000, pp. 577–588.
[2] Y.-J. Huang and J.-F. Li, “Testability exploration of 3-D RAMs and CAMs,” in IEEE Asian Test Symp. (ATS), Nov 2009, pp. 397–402.
[3] J.-F. Li, R.-S. Tzeng, and C.-W. Wu, “Testing and diagnosing embedded content addressable memories,” in Proc. IEEE VLSI Test Symp. (VTS), 2002, pp. 389–394.
[4] I. Kim, Y. Zorian, G. Komoriya, H. Pham, F. Higgins, and J. Lewandowski, “Built in self repair for embedded high density SRAM,” in Proc. Int’l Test Conf. (ITC), Oct
1998, pp. 1112–1119.
[5] T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, “A built-in self-repair analyzer (CRESTA) for embedded DRAMs,” in Proc. Int’l Test Conf. (ITC),
2000, pp. 567–574.
[6] V. Schober, S. Paul, and O. Picot, “Memory built-in self-repair using redundant words,” in Proc. Int’l Test Conf. (ITC), 2001, pp. 995–1001.
[7] Y. Zorian and S. Shoukourian, “Embedded-memory test and repair: infrastructure IP for SoC yield,” IEEE Design & Test of Computers, vol. 20, no. 3, pp. 58–66, May 2003.
[8] C.-L. Su, R.-F. Huang, and C.-W. Wu, “A processor-based built-in self-repair design for embedded memories,” in IEEE Asian Test Symp. (ATS), Nov 2003, pp. 366–371.
[9] S.-K. Lu, Y.-C. Tsai, C.-H. Hsu, K.-H. Wang, and C.-W. Wu, “Efficient built-in redundancy
analysis for embedded memories with 2-D redundancy,” IEEE Trans. on VLSI Systems, vol. 14, no. 1, pp. 34–42, Jan 2006.
[10] J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu, “A built-in self-repair design for RAMs with 2-D redundancy,” IEEE Trans. on VLSI Systems, vol. 13, no. 6, pp. 742–745, June 2005.
[11] C.-D. Huang, J.-F. Li, and T.-W. Tseng, “ProTaR: an infrastructure IP for repairing RAMs in system-on-chips,” IEEE Trans. on VLSI Systems, vol. 15, no. 10, pp. 1135–
1143, Oct 2007.
[12] T.-W. Tseng, J.-F. Li, and C.-C. Hsu, “ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SoCs,” IEEE Trans. on VLSI Systems, vol. 18, no. 6, pp. 921–932, June 2010.
[13] T.-W. Tseng, Y.-J. Huang, and J.-F. Li, “DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs,” IEEE Trans. on Computer-Aided Design
of Integrated Circuits and Systems, vol. 29, no. 10, pp. 1628–1639, Oct 2010.
[14] J.-F. Li, T.-W. Tseng, and C.-S. Hou, “Reliability-enhancement and self-repair schemes for SRAMs with static and dynamic faults,” IEEE Trans. on VLSI Systems, vol. 18,
no. 9, pp. 1361–1366, Sept 2010.
[15] T.-W. Tseng, J.-F. Li, and C.-S. Hou, “A built-in method to repair SoC RAMs in parallel,” IEEE Design & Test of Computers, vol. 27, no. 6, pp. 46–57, Nov 2010.
[16] Y.-J. H. Chun-Kai Lai and J.-F. Li, “A self-repair technique for content addressable memories with address-input-free writing function,” Journal of Information Science and Engineering, vol. Volume 29, no. 3, pp. 493–507, May 2013.
[17] H.-H.Wu, J.-N. Lee, M.-C. Chiang, P.-W. Liu, and C.-F.Wu, “A comprehensive TCAM test scheme: an optimized test algorithm considering physical layout and combining scan
test with at-speed BIST design,” in Proc. Int’l Test Conf. (ITC), Nov 2009, pp. 1–10.
[18] J.-F. Li, R.-S. Tzeng, and C.-W. Wu, “Testing and diagnosis methodologies for embedded content addressable memories,” Journal of Electronic Testing, vol. Volume 19, pp. pages 207–215, 2003.
[19] H. Noda, K. Inoue, M. Kuroiwa, F. Igaue, K. Yamamoto, H. Mattausch, T. Koide, A. Amo, A. Hachisuka, S. Soeda, I. Hayashi, F. Morishita, K. Dosaka, K. Arimoto, K. Fujishima, K. Anami, and T. Yoshihara, “A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture,” IEEE Jour. of Solid-State Circuits, vol. 40, no. 1, pp. 245–253, Jan 2005.
[20] R. Nadkarni, I. Arsovski, R. Wistort, and V. Chickanosky, “Improved match-line test and repair methodology including power-supply noise testing for content-addressable memories,” in Proc. Int’l Test Conf. (ITC), Oct 2006, pp. 1–9.
[21] G.-Q. Lin, Z.-Y. Wang, and S.-K. Lu, “Built-in self-repair techniques for content addressable memories,” in Proc. IEEE Int. Symp. on VLSI Design, Automation, and Test
(VLSI-DAT), April 2009, pp. 267–270.
[22] R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W.Wu, “A simulator for evaluating redundancy analysis algorithm of repairable embedded memories,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), 2002, pp. 68–73.
指導教授 李進福(Jin-Fu Li) 審核日期 2016-1-27
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