博碩士論文 101521105 詳細資訊




以作者查詢圖書館館藏 以作者查詢臺灣博碩士 以作者查詢全國書目 勘誤回報 、線上人數:29 、訪客IP:34.234.207.100
姓名 丁玄峰(Huasn-Feng Ting)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 具多斜率展頻技術之低電磁干擾降壓轉換器
(A Low EMI DC-DC Buck Converter with Multiple-Slopes Spread-spectrum Clock Technique)
相關論文
★ 一種應用於觸控液晶顯示器的新型嵌入式開關★ 多重相位之延遲鎖定迴路倍頻器設計與分析
★ 2.5Gbps串列收發器設計★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路★ 全數位任意責任週期之同步映射延遲電路
★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統
★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路★ 高解析度可變動責任週期之同步複製延遲電路
★ 奈米CMOS晶片內序列傳輸之接收器★ 奈米CMOS晶片內序列傳輸之送器
★ 基於鎖相迴路之多重相位脈波產生器★ 低能量時脈儲存元件之分析、設計與量測
★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計
檔案 [Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載]
  1. 本電子論文使用權限為同意立即開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。

摘要(中) 切換式穩壓器會產生傳導性的電磁干擾,在國際無線電干擾特別委員會將規範其電
磁干擾量,故本論文提出一個輸入為1.8 V 輸出為1 V 的降壓轉換器、擁有兩種不同展
頻模式之多斜率展頻技術之低電磁干擾降壓轉換器。在此設計中,本設計使用含有多頻
率馳張震盪器,因此可在產生不同的頻率達到降低電磁干擾之功能。提出一個可切換斜
率的展頻控制希望可以讓電磁干擾抑制效果更佳。使用不同斜率的展頻模式會產生不同
的抑制效果,藉著比較不同的展頻模式得到一個良好的展頻效果。
本論文之具多斜率展頻技術之低電磁干擾降壓轉換器使用180 nm 1.8 V CMOS 製
程實現晶片,其操作頻率為1 MHz,並且擁有兩種展頻模式。電路在展頻範圍為1 MHz
時三角波調變展頻機制對於電磁干擾之抑制量為10.96 dB,而使用三斜率展頻之電磁干
擾抑制量為15.98 dB,展頻範圍為1.33 MHz 時三角波調變展頻機制對於電磁干擾之抑
制量為16.35 dB,而使用三斜率展頻之電磁干擾抑制量為24.63 dB,整體晶片面積為1200
× 1190 um2。
摘要(英) A Low EMI DC-DC Buck Converter with Multiple-Slopes Spread-spectrum Clock Technique with 1 voltage output has been presented in this thesis. A multi- frequency relaxation oscillator with switching capacitor has been used in this design and this circuit can be operating at difference frequency. The proposed spread-spectrum clock technique can switch slop and generate multi-frequency. The triple slop mode used in the spread-spectrum mechanism increases the more reduction of electromagnetic interference with comparison to other modulations.
The proposed A Low EMI DC-DC Buck Converter with Multiple-Slopes Spread-spectrum Clock Technique has been fabricated in 180 nm 1.8 V CMOS process. The reduction of electromagnetic interference are 16.35 dB with the spread-spectrum mechanism modulated by triangular mode 24.63 dB with the spread-spectrum mechanism modulated by triple slop mode. The chip area is 1200 × 1190 um2 .
關鍵字(中) ★ 切換式穩壓器
★ 展頻技術
★ 降壓轉換器
★ CISPR22
關鍵字(英) ★ DC–DC Converter
★ Spread-spectrum Clock Technique
★ Buck Converter
★ 國際無線電干擾 特別委員會
論文目次 摘要 I
Abstract II
誌謝 III
目錄 IV
圖目錄 VII
表目錄 X
第1章 緒論 1
1.1 研究動機 1
1.2 研究目的及其應用 2
1.3 論文架構 3
第2章 低雜訊切換式降壓穩壓器先前技術探討 5
2.1 電磁干擾(Ectromagnetic interference)簡介 5
2.2 展頻時脈產生器簡介 7
2.3 先前技術探討 8
2.3.1 利用跳頻降低電磁干擾之直流轉換器(Spur-Reduction Design of Frequency-Hopping DC–DC Converters)[3] 8
2.3.2 使用Delta–Sigma調變器之雜訊整型技術(A Noise-Shaped Switching Power Supply Using a Delta–Sigma Modulator)[4] 9
2.3.3 使用隨機切換頻率降低電磁干擾之轉換器(Random Switching Frequency Buck Converter for Conductive EMI Reduction)[5] 10
2.4 預計論文規格 12
第3章 低雜訊切換式降壓轉換電路設計 15
3.1 系統架構 15
3.2 小信號分析[6] 16
3.2.1 電壓模式模型分析 16
3.3 展頻控制電路(Spread-spectrum controller) 24
3.3.1 展頻機制 (Spread-spectrum) 24
3.3.2 馳張震盪器(Relaxation oscillator) 25
3.3.3 斜率選擇器 (Slope selector) 26
3.3.4 斜率偵測器 (Slope detector) 27
3.3.5 斜率切換器 (Slope switch) 28
3.3.6 上下數計數器 (Up/Down counter) 29
3.4 帶差參考電路 (Band gap reference) 30
3.5 誤差放大器(Error amplifier ) 32
3.6 比較器電路(Comparator circuit) 32
3.7 緩啟動電路(Soft start circuit) 33
第4章 行為模擬及參數分析 35
4.1 行為模擬架構圖 35
4.1.1 電磁干擾抑制量與展頻階數之關係 36
4.1.2 電磁干擾抑制量與斜率之關係 39
4.1.3 展頻參數之選擇 42
第5章 電路模擬與晶片量測結果 45
5.1 設計流程 45
5.2 佈局後電路模擬 45
5.2.1 帶差參考電路模擬結果 45
5.2.2 誤差放大器模擬結果 46
5.2.3 輸出漣波及其頻譜模擬 47
5.3 電路佈局 51
5.4 晶片照相與量測環境設定 54
5.5 量測結果 55
5.6 規格比較 62
第6章 結論與未來研究方向 65
6.1 結論 65
6.2 未來研究方向 65
參考文獻 67


參考文獻 參考文獻
[1] T. Sakurai, “Low power digital circuit design,” IEEE European Solid-State Circuits Conference, pp. 11-18, Sep. 2004.
[2] F. S. L. J. Breems, K. A. A. Makinwa, S. Drago, D. M. W. Leenaerts, and B. Nauta, “A low-voltage mobility-based frequency reference for crystal-less ULP radios,” IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 2002–2009, July. 2009.
[3] M. S. McCorquodale, J. D. O′Day, S. M. Pernia, G. A. Carichner, S. Kubba, R. B. Brown, "A monolithic and self-referenced RF LC clock generator compliant with USB 2.0," IEEE J. Solid-State Circuits, vol. 42, pp. 385-399, Feb 2007.
[4] V. D. Smedt, P. D. Wit, W. Vereecken, and M. S. J. Steyaert, “A 66 uW 86 ppm/°C fully-Integrated 6 MHz wienbridge oscillator with a 172 dB phase noise FOM,” IEEE J. Solid-state Circuits, vol.44, no. 7, pp. 1990-2001, Jul. 2009.
[5] J. Lee and S. Cho, “A 10MHz 80μW 67 ppm/°C CMOS reference clock oscillator with a temperature compensated feedback loop in 0.18μm CMOS,” in Proc. IEEE Symp. on VLSI, 2009, pp. 226–227.
[6] S. L. J. Gierkink and Ed (A. J. M.) v. Tuijl, “A coupled sawtooth oscillator combining low jitter with high control linearity,” IEEE J. Solid-state Circuits, vol.37, no. 6, pp. 702-710, Jun. 2002.
[7] J.-C. Liu, W.-C. Lee, H.-Y. Huang, K.-H. Cheng, C.-J. Huang, Y.-W. Liang, J.-H. Peng, and Y.-H. Chu, “A 0.3-V all digital crystal-less clock generator for energy harvester applications,” in proc. Asian Solid-State Circuits Conference, 2012, pp.117-120.
[8] U. Denier, “Analysis and design of an ultralow-power CMOS relaxation oscillator,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 8, Aug. 2010.
[9] Y.-C. Shih and B. Otis, “An on-chip tunable frequency generator for crystal-less low-power WBAN radio,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 60, no. 4, Apr. 2013.
[10] Y. Tokunaga, S. Sakiyama, A. Matsumoto, and S. Dosho, "An on-chip CMOS relaxation oscillator with voltage averaging feedback", IEEE J. Solid-State Circuits, vol. 45, no. 6, pp.1150 -1158, 2010.
[11] F. Sebastiano , L. Breems , K. Makinwat , S. Drago , D. Leenaerts and B. Nauta, ”A 65-nm CMOS temperature-compensated mobility-based fre- quency reference for wireless sensor networks,” IEEE J. Solid-State Circuits, vol. 45, no. 7, pp. 1544–1552, July. 2011.
[12] M. S. McCorquodale, S. M. Pernia, J. D. O’Day, G. Carichner, E. Marsman, N. Nguyen, S. Kubba, S. Nguyen, J. Kuhn, and R. B. Brown, “A 0.5-to- 480MHz self-referenced CMOS clock generator with 90ppm total frequency error and spread-spectrum capability,” in IEEE ISSCC Dig. Tech. Papers, pp. 350-351, 2008.
[13] W.-H. Sung, S.-Y. Hsu, J.-Y. Yu, C.-Y. Yu, and C.-Y. Lee, “A frequency accuracy enhanced sub-10uW on-chip clock generator for energy Efficient crystal-less wireless biotelemetry applications,” in Proc. IEEE Symp. on VLSI, 2010, pp. 115–116.
[14] H.-Y. Huang, and F.-C. Tsai, ‘‘Analysis and optimization of ring oscillator using sub-feedback scheme,’’ in Proc. IEEE Int. Symp. Design and Diagnostics of Electronic Circuits and Systems, Apr. 2009, pp. 28-29.
[15] Yong-Jhen Jhu,2011,‘‘A 4-GHz 10-Phase all digital phase-locked loop’’, NCU M. Thesis, Oct. 2011.
[16] P. Dudek, S. Szczepanski, and J. Hatfield, ” A high-resolution CMOS time -to-digital converter utilizing a vernier delay line,” IEEE J. Solid-state Circuits, vol.35, pp. 240-247, Feb. 2000.
[17] A. H. Chan, and G.W. Roberts “A deep sub-micron timing measurement circuit using a single-stage vernier delay line,” IEEE Proc. CICC, pp. 77-80, May 2002.
[18] H.-Y. Huang, W.-C. Hung, H.-W. Cheng, and C.-H. Lu, “All digital time-to-digital converter with high resolution and wide detect range,” Engineering Letters, Aug. 2011.
[19] V. Kratyuk, ‘‘Digital phase-locked loops for multi-GHz clock generation,” OSU Ph. D. Thesis, Dec. 2006.
[20] M. Kashmiri, M. Pertijs, and K. Makinwa, “A thermal-diffusivity-based frequency reference in standard CMOS with an absolute inaccuracy of ±0.1% from -55°C to 125°C,” IEEE J. Solid-state Circuits, vol.45, pp.2510-2520, Dec 2010.
[21] K.-H. Cheng, C.-C. Hu, J.-C. Liu, and H.-Y. Huang, “A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop,” in Proc. IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems, Apr. 2010, pp. 285-288
[22] W.-H. Sung, J.-Y. Yu, and C.-Y. Lee, “A robust frequency tracking loop for energy-efficient crystal-less WBAN system,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 58, no. 10, Oct. 2011.
[23] K. Sundaresan, P. E. Allen, and F. Ayazi, “Process and temperature compensation in a 7-MHz CMOS clock oscillator,” IEEE J. Solid-state Circuits, vol.41, no. 2, pp. 433-442, Feb. 2006.
[24] Y. Tokunaga, S. Sakiyama, A. Matsumoto, and S. Dosho, “An on-chip CMOS relaxation oscillator with power,” in IEEE ISSCC Dig. Tech. Papers, pp. 404-405, 2009.
[25] P. F. J. Geraedts, E. v. Tuijl, E. A. M. Klumperink, G. J. M. Wienk, and B. Nauta, “A 90µW 12MHz relaxation oscillator with a -162dB FOM,” in IEEE ISSCC Dig. Tech. Papers, pp. 348-349, 2008.
[26] K. Choe, O. D. Bernal, D. Nuttman2, and M. Je, “A precision relaxation oscillator with a self-clocked offset-cancellation scheme for implantable biomedical SoCs,” in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 402–403.
[27] M. Kashmiri, M. Pertijs, and K. Makinwa “A thermal-diffusivity-based frequency reference in standard CMOS with an absolute inaccuracy of ±0.1% from -55°C to 125°C,” in IEEE ISSCC Dig. Tech. Papers, 2010, pp. 74–75.
[28] Y. Lu, G. Yuan, L. Der, W.-H. Ki, and C. P. Yue, “A ±0.5% precision on-chip frequency reference with programmable switch array for crystal-less applications” IEEE Trans. Circuits Syst. II, Exp. Briefs, to be published.
[29] L. Zhou, M. Annamalai, J. Koh, M. Je, L. Yao, and C.-H. Heng,”A crystal- less temperature-independent reconfigurable transmitter targeted for high-temperature wireless acoustic telemetry applications,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 9, Sep. 2013.
指導教授 鄭國興(Kuo-Hsing Cheng) 審核日期 2015-8-20
推文 facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu   
網路書籤 Google bookmarks   del.icio.us   hemidemi   myshare   

若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡  - 隱私權政策聲明