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姓名	楊其峻(Chi-Chun Yang)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	應用於動態隨機存取記憶體之混合式自我測試方法 (A Hybrid Built-In Self-Test Scheme for DRAMs)
相關論文	★ 應用於三元內容定址記憶體之低功率設計與測試技術 ★ 用於隨機存取記憶體的接線驗證演算法 ★ 用於降低系統晶片內測試資料之基礎矽智產 ★ 內容定址記憶體之鄰近區域樣型敏感瑕疵測試演算法 ★ 內嵌式記憶體中位址及資料匯流排之串音瑕疵測試 ★ 用於系統晶片中單埠與多埠記憶體之自我修復技術 ★ 用於修復嵌入式記憶體之基礎矽智產 ★ 自我修復記憶體之備份分析評估與驗證平台 ★ 使用雙倍疊乘累加命中線之低功率三元內容定址記憶體設計 ★ 可自我測試且具成本效益之記憶體式快速傅利葉轉換處理器設計 ★ 低功率與可自我修復之三元內容定址記憶體設計 ★ 多核心系統晶片之診斷方法 ★ 應用於網路晶片上隨機存取記憶體測試及修復之基礎矽智產 ★ 應用於貪睡靜態記憶體之有效診斷與修復技術 ★ 應用於內嵌式記憶體之高效率診斷性資料壓縮與可測性方案 ★ 應用於隨機存取記憶體之有效良率及可靠度提升技術
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摘要(中)	動態隨機存取記憶體（DRAM）在電子系統中扮演著重要的角色。近來，多通道動態隨機存取記憶體已被應用於三維或2.5維晶片中。由於多通道動態隨機存取記憶體在三維或2.5維晶片中測試操作困難，內建自我測試電路（built-in self-test）被視為一個好的測試方法。不同的內建自我測試電路已經被廣泛應用於動態隨機存取記憶體的測試。在先前已經有許多內建自我測試電路的技術被提出，而其大部分設計成可程式化（programmability）來支援不同的測試演算法。 在本論文中，我們首先針對各種應用於隨機存取記憶體的可程式化內建自我測試電路做探討。並且對於不同的可程式化內建自我測試電路進行詳盡的分析。隨後，我們提出了一個應用於動態隨機存取記憶體的混合式內建自我測試方法。所提出的混合式自我測試電路包含了一個支援對於金屬光罩改變（metal-change） 可程式化的微指令形式控制器（microcode-based controller） 和支援對於使用中模式暫存器和型態參數可程式化的有限狀態機形式控制器（FSM-based controller）。因此，如果所需的測試演算法沒有被預先存在唯讀記憶體中 （read-only-memory），我們僅需要改變金屬光罩來改變支援的測試演算法。現場可程式化可以滿足堆疊後測試（post-bond test）的需求，例如：驅動能力、 熱補償、不同個數的堆疊晶粒等。而我們也實際做出了應用於一個多通道動態隨機存取記憶體的混合式內建自我測試電路。實驗結果顯示，當應用在一個20Gb 4-通道動態隨機存取記憶體中單通道且支援行軍式（March）和非行軍式演算法與使用TSMC 90nm的製程時，我們的混合式自我測試電路僅需要18.2K邏輯閘數。最後，我們提出了一個應用於動態隨機存取記憶體的記憶體內建自我測試電路編譯器（compiler）。提出的內建自我測試電路編譯器可以產生出不同形式的內建自我測試電路，包括有限狀態機形式、微指令形式、可程式化微指令形式和我們所提出的混合式內建自我測試電路。
摘要(英)	Dynamic random access memory (DRAM) is one key component in electronic systems. Recently, multi-channel DRAMs have been proposed for three dimensional (3D) or 2.5D chips. Due to the poor test accessibility, built-in self-test (BIST) method is considered a good approach for the postbond testing of multi-channel DRAMs in 2.5D/3D chips. Various BIST schemes were presented to test DRAMs. To support different test algorithms, most of those BISTs are designed as they have the programmability of test algorithms. In this thesis, we first survey existing programmable BIST schemes for RAMs. Comparison of different programmable BISTs is conducted . Then, a hybrid BIST scheme for DRAMs is proposed. The hybrid BIST consists of a microcode-based controller for supporting the metal-change programmability of test algorithms and an FSM-based controller for supporting the in-field programmability of mode registers and configuration parameters. Thus, if the needed test algorithms are out of the test algorithms stored in the read-only-memory, only metal changing is needed to change the supported test algorithms. The in-field programmability can meet the requirement of post-bond test on the uncertainties of test thermal, number of stacked dies, driving strength of drivers, and so on. We also have implemented the hybrid BIST for a multi-channel DRAM. Simulation results show that only about 18.2K gates are needed to support March and non-March test algorithms for a single channel within a 20Gb 4-channel DRAM using TSMC 90nm standard cell library. Finally, a memory BIST compiler for DRAMs is proposed. The memory BIST compiler can generate different types of memory BISTs including the FSM-based, microcode-based, microcode programmable, and proposed hybrid BISTs.
關鍵字(中)	★ 內建自我測試電路	關鍵字(英)	★ BIST
論文目次	1 Introduction 1 1.1 Dynamic Random Access Memory (DRAM) . . . . . . . . . . . . . . . . . . . . 1 1.2 Existing Built-In Self-Test Techniques . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 BIST Challenges of Modern DRAMs . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3.1 DQ Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3.2 Double Edge-trigger Issue . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.3 Burst Length for Diagnostic Data Exportation . . . . . . . . . . . . . . . . 7 1.3.4 Overflow of ATE Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.5 Critical DRAM Access Mode, Power and Test Condition . . . . . . . . . . 8 1.4 Thesis Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Survey of Programmable BIST Schemes for DRAMs 12 2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 Reviews of Various Programmable BIST Schemes . . . . . . . . . . . . . . . . . . 12 2.2.1 Programmable FSM-based BIST . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 Microcode-based BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.3 Microcode Programmable BIST . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 A Hybrid Built-In Self Test Scheme for DRAMs 21 3.1 Why Hybrid BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 Proposed Hybrid BIST Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.1 Overall Test Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.2 BIST Command and Microcode Instruction . . . . . . . . . . . . . . . . . 24 3.2.3 Hybrid BIST Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2.4 Hybrid BIST Operation Flow . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2.5 Programmability of Test Algorithms and Example . . . . . . . . . . . . . 41 3.3 Simulation and Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3.1 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3.2 Bandwidth Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.3 Different Types of BIST Schemes . . . . . . . . . . . . . . . . . . . . . . 49 3.4 Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4 A Compiler of Programmable BIST for DRAMs 54 4.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.2 Proposed Memory BIST Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2.1 Proposed BIST Templates . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2.2 ROM Information Generator . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.2.3 BIST Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.2.4 Compilation Flow of Proposed Memory BIST Compiler . . . . . . . . . . 62 4.3 Experimental and Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . 62 4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5 Conclusion and FutureWork 67 5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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指導教授	李進福(Jin-Fu Li)	審核日期	2015-8-27
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