適用於混合訊號設計的自動化電路區塊行為模型產生器

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：45

、訪客IP：3.147.44.146

姓名

王綉文(Shiou-Wen Wang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用於混合訊號設計的自動化電路區塊行為模型產生器
(Automatic Behavioral Model Generation for Circuit Blocks in Mixed-Signal Designs)

相關論文

★ 運算放大器之自動化設計流程及行為模型研究	★ 高速序列傳輸之量測技術
★ 使用低增益寬頻率調整範圍壓控震盪器之1.25-GHz八相位鎖相迴路	★ 類神經網路應用於高階功率模型之研究
★ 使用SystemC語言建立IEEE 802.3 MAC 行為模組之研究	★ 以回填法建立鎖相迴路之行為模型的研究
★ 高速傳輸連結網路的分析和模擬	★ 一個以取樣方式提供可程式化邏輯陣列功能除錯所需之完全觀察度的方法
★ 抑制同步切換雜訊之高速傳輸器	★ 以行為模型建立鎖相迴路之非理想現象的研究
★ 遞迴式類神經網路應用於序向電路之高階功率模型的研究	★ 用於命題驗証方式的除錯協助技術之研究
★ Verilog-A語言的涵蓋率量測之研究	★ 利用類神經模型來估計電源線的電流波形之研究
★ 5.2GHz CMOS射頻接收器前端電路設計	★ 適用於OC-192收發機之頻率合成器和時脈與資料回復電路

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

隨著主流單晶片系統設計(system-on-chip, SoCs)的複雜度日益提升，以及因應逐漸縮短的緊迫上市時間(time-to-market)，晶片設計者可能缺乏時間成本反覆進行完整的測試。此外，類比與數位混合訊號(analog and mixed signal, AMS)元件在SoC晶片中的地位越來越重要，據統計所佔比重約有30~50%，且有高達50%的驗證錯誤是源自於類比混合訊號區塊，需要消耗時間與成本進行再設計(redesign)。基於上述的理由，系統層級的驗證在現今的設計流程中扮演極重要的角色。
為了加速類比混合訊號電路的驗證，現行常見的解決方法為提升電路階層層級(hierarchy)，使用硬體描述語言(hardware description language, HDL)建立小區塊電路的行為模型(behavioral model)。現存的行為模型研究大多侷限於特定電路架構，如：鎖相迴路(Phase Locked Loop, PLL)、運算放大器(Operational Amplifier, OPA)或射頻傳輸線(RF transmission line)等重複性高的折疊式(cascode)電路；至於電路區塊間用來溝通訊號的連結邏輯(glue logic)，則較少文獻著墨於此種非特定架構模型產生器(model generator)的方法研究。
有鑑於此，本論文致力於行為模型產生器的建構，透過輸入電晶體層級的電路描述，取得電路的初始行為，再經過一連串的電路資訊分析與訊號流上的架構辨識，最終自動產出Verilog語言編寫成的近似行為模型，且與原電路行為的差異控制在很小的誤差範圍內。

摘要(英)

With the ever-increasing complexity of system-on-chip (SoCs) and the rapidly decreasing time-to-market, IC designers may not afford repeated full testing. Besides, the proportion of analog and mixed signal (AMS) elements in current SoCs has risen to 30 to 50%, and about 50% of errors that required redesign are owing to AMS parts. As a result, system-level verification takes an important role in today’s industry design flow.
To speed up the co-simulation of AMS circuits, modeling circuit blocks by hardware description languages is a common trend to give rise to hierarchy. An abundance of methodology has been proposed to deal with application speciﬁc integrated circuit (ASIC) modeling, such as PLL, OPA, or cascade circuits like RF transmission line. However, there’s few approach concerning about the modeling of glue logics, which are simple logicsor unspecific small circuit blocks used to connect complex circuits together.
This thesis presents a model generator, using simple methods to extracting behaviors from transistor-level descriptions. By analyzing circuit information from recognized structures along signal graph, this model generator eventually produces approximated behavioral model in Verilog within tolerable error range.

關鍵字(中)

★ 設計自動化
★ 行為模型
★ 混合訊號

關鍵字(英)

★ Design Automation
★ Behavioral Modeling
★ Mixed-Signal

論文目次

摘要 .............................................................. i
Abstract.......................................................... ii
致謝 ............................................................ iii
目錄 ............................................................. iv
圖目錄 ........................................................... vi
表目錄 ............................................................ x
1. 第一章、緒論 .................................................. 1
1-1 研究動機 ........................................................................................................1
1-2 行為模式(Behavioral Modeling) ...................................................................5
1-3 論文結構 ........................................................................................................8
2. 第二章、背景知識 .............................................. 9
2-1 宏模型簡介(Macromodel).............................................................................9
2-2 符號函式方法(Symbolic Approach)............................................................12
2-2-1 行列式判定圖基礎(Determinant Decision Diagram, DDD-based)方
法..................................................................................................................14
2-3 演算式方法(Algorithmic Approach) ...........................................................16
2-3-1 片段線性估算法(Piecewise Approximation Methods)....................21
2-4 回歸分析 (Regression)................................................................................23
2-4-1 移動平均濾波 (Moving Average, MA)...........................................24
2-4-2 離散時間傅立葉轉換 (Discrete-Time Fourier Transform, DTFT).25
2-4-3 薩維基‧格雷摺積平滑(Savitzky–Golay, SG)................................26
2-5 問題定義 ......................................................................................................28
3. 第三章、二階段式行為模型產生器 ............................... 30
3-1 二階段式行為模型產生器流程 ..................................................................30
3-2 行為萃取(Behavior Extraction) ...................................................................31
3-2-1 架構分析(Structural Analysis)..........................................................31
3-2-2 同構關係(Isomorphism)...................................................................32
3-2-3 對稱關係(Symmetry)........................................................................35
3-2-4 優勢圖(Dominance Graph)...............................................................37
3-3 初始模型建立(Initial Model Construction).................................................39
3-3-1 改進架構信號流圖(Enhanced Structural Signal Flow Graph, ESFG)
......................................................................................................................40
3-4 矩陣運算(Matrix Calculation) .....................................................................42
3-4-1 修正節點分析(Modified Nodal Analysis, MNA) ............................43
3-4-2 微分方程(Differential Algebraic Equations, DAE)函數選擇..........47
3-5 曲線平滑(Curve Smoothing) .......................................................................48
4. 第四章、實驗結果 ............................................. 54
4-1 環境設定 ......................................................................................................54
4-2 架構分析結果 ..............................................................................................56
4-3 實驗結果 ......................................................................................................58
5. 第五章、結論與未來研究方向 ................................... 64
6. 第六章、參考文獻 ............................................. 65

參考文獻

[1] Available on http://www.cadence.com/community/blogs/ii/archive/2011/06/13/dac-panel-users-describe-mixed-signal-verification-challenges-solutions.aspx
[2] Available on http://www.cadence.com/Community/blogs/ii/archive/2011/02/20/analog-mixed-signal-behavioral-modeling-when-to-use-what.aspx
[3] A. Mantooth, et.al, “Modelling tools built upon the hardware description language foundation”, Computers & Digital Techniques, IET, pp.519-527, Sep. 2007
[4] R. A. Rutenbar, et.al, “Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs”, Proceedings of the IEEE, pp. 640-669, Mar. 2007
[5] C. Borchers, “Symbolic behavioral model generation of nonlinear analog circuits”, Circuits and Systems II , pp. 1362- 1371, Oct. 1998.
[6] P. Wambacq, et.al, “Efficient symbolic computation of approximated small-signal characteristics,” IEEE J. Solid-State Circuits, pp. 327-330, Mar. 1995.
[7] C. -J. R. Shi, X. D. Tan, “Canonical symbolic analysis of large analog circuits with determinant decision diagrams”, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, pp. 1-18, Jan. 2000
[8] C. -J. R. Shi, X. D. Tan, “Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design”, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, pp. 813-827, Oct. 2001
[9] G, Vandersteen., “Nonlinear distortion analysis incircuits and systems-Demystification of nonlinear systems”, tutorial T11, International Symposium on Circuits and Systems, Jun. 2014
[10] L. T. Pillage, R. A. Rohrer, “Asymptoticwaveform evaluation for timing analysis”, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, pp. 352-366, Apr. 1990
[11] J.R. Li, J. White, “Efficient modelreduction of interconnect via approximatesystem gramians”, International Conference on Computer-Aided Design, pp. 380-383, Nov. 1999
[12] K. Gallivan, et.al, ”Asymptotic waveform evaluation via aLanczos method”, Applied Mathematics Letters, pp. 75–80, Sep. 1994
[13] J. Katzenelson and L. H. Seitelman, “Aniterative method for solution of nonlinearresistive networks”, AT&T Bell Laboratories,Tech. Rep. TM65-1375-3.
[14] A. Demir, J. Roychowdhury, "A reliable and efficient procedure for oscillator PPV computation, with phase noise macromodeling applications," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, pp.188-197, Feb. 2003
[15] F. Mourad, et.al, “Analog/RF and Mixed-Signal Circuit Systematic Design”, ISBN 978-3-642-36329-0, pp. 22-23.
[16] M. Rewienski, J. White, "A trajectory piecewise-linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, pp.155-170, Feb. 2003
[17] N. Dong, J. Roychowdhury, "Piecewise polynomial nonlinear model reduction," Design Automation Conference, pp.484-489, June 2003
[18] Available on http://www.analog.com/static/imported-files/tech_docs/dsp_book_Ch15.pdf
[19] R.W. Schafer, “WhatIsaSavitzky-GolayFilter?”, IEEE Signal Processing Magazine, pp.111-117, 2011
[20] A. Savitzky, M. J. E. Golay, “Smoothing and Differentiation of Data by Simplified Least Squares Procedures,” Analytical Chemistry, pp 1627–1639, July 1964
[21] CIC 國家晶片系統設計中心, “Hspice Tutorial”, https://sites.google.com/site/ykcycuee/tutorial/eda-tools/hspice-tutorial
[22] M. Eick, “Structure and Signal Path Analysis for Analog and Digital Circuits”, TUM, Dep. EE&IT (ISBN 978-3-8349-1114-6)
[23] T. Massier, et.al, "The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.27, no.12, pp.2209-2222, Dec. 2008
[24] Y. C. Liao, et.al, “LASER: layout-aware analog synthesis environment on laker”, Great Lakes Symposium on VLSI, pp.107-112, May 2013
[25] 微分方程(ODEs)解算器(Solver)的介绍, Matlab技術論壇, http://www.matlabsky.com/thread-528-1-1.html
[26] C. M. Bishop, “Polynomial Curve Fitting”, Pattern Recognition and Machine Learning (Information Science and Statistics), ISBN-10: 0387310738, ch.1.1, 2007.
[27] Available on http://fac2013.imag.fr/FINAL/Eickposter.pdf

指導教授

劉建男(Chien-Nan Liu)

審核日期

2014-8-27

推文