博碩士論文 101522085 詳細資訊




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姓名 陳泓霖(Hung-lin Chen)  查詢紙本館藏   畢業系所 資訊工程學系
論文名稱 物件偵測嵌入式硬體加速器設計與實作
(Design and Implementation of Hardware Accelerator for Embedded Object Detection)
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摘要(中) 在現今機器視覺系統多以SoC嵌入式軟硬體整合方法設計,使用FPGA取代多個DSP模組。在傳統的開發中,通常依據需求先設計軟體雛型,接著再將某些模組硬體化,達成軟硬體共同設計之系統。硬體模組多以連續串流進行設計,然而這種方法較缺乏彈性,當需求只要小小改變時,整個硬體模組可能就不適用需要重新規劃。
本論文提出嵌入式視覺軟硬體設計方法論,以IDEF0進行系統分析,將需求階層式模組化切割為多個子模組,再以Grafcet建立各個子模組的離散事件模型,透過快速對應產生軟體語言及硬體語言,此方法論的優點是開發者在系統開發前期不需撰寫程式。另外本論文提出硬體介面控制器,針對軟硬體共同設計之平台,在開發者針對不同目標需求(效能、彈性、成本、耗電)選用硬體模組時,不必重新規劃硬體模組間的設計,只需要透過軟體控制即可規劃硬體模組執行之順序,增加硬體模組之開發彈性,加快系統開發流程。
摘要(英) In recent years, most of the machine vision systems use embedded hardware and software co-design, which uses FPGA to replace some DSP modules. In traditional development, we first design software prototype and then choose some modules that designed by hardware. We use a series designed to connect this hardware modules to compose hardware architecture. However, this type of architecture lacks flexibility. If system requirements just need to do a little change, the architecture need to whole redesign.
In this thesis, we propose embedded vision hardware and software co-design methodology. Firstly, we analyze the system requirements with IDEF0. This way is analysis whole system hierarchically and divided into many modules. Secondly, we use Grafcet establish discrete event model for every modules. Then we through the way of Grafcet synthesis to produce software code and hardware design. This development approach needs not coding in prophase of system design. Additionally, we design a hardware interface controller, which is suitable in hardware and software co-design architecture. This controller contains all of hardware modules, and designers can select desired target modules according to system requirements which include efficacy, elasticity, cost, and power consumption. It is not necessary to redesign hardware architecture, the designer just to change the order of hardware modules through software. The hardware interface controller can increased development flexibility, and accelerate the system development process.
關鍵字(中) ★ 軟硬體共同設計 關鍵字(英)
論文目次 摘 要 I
ABSTRACT V
目錄 VI
圖目錄 IX
表目錄 XII
第一章、緒論 1
1.1 研究背景 1
1.2 研究目的 2
1.3 論文架構 4
第二章、文獻回顧 5
2.1 軟硬體共同設計 5
2.2 嵌入式影像處理 10
2.2.1 形態學影像處理 10
2.2.2 影像切割 11
2.2.3 連通元件 13
第三章、嵌入式硬體加速器設計方法論 16
3.1 規格定義與功能描述 16
3.2 嵌入式系統設計方法論 17
3.2.1 IDEF0 18
3.2.2 Grafcet 19
3.2.3 GRAFCET軟體及硬體合成 23
3.3 軟硬體整合 25
3.3.1 硬體加速器 25
3.3.2 介面控制器 26
3.3.3 軟體層 28
第四章、物件偵測嵌入式硬體加速器設計 30
4.1 實驗平台 30
4.2 系統需求分析及IDEF0架構設計 31
4.3 離散事件建模 32
4.3.1 背景建模 33
4.3.2 物件切割 36
4.3.2.1 前景分割 37
4.3.2.2 斷開法 39
4.3.2.3 連通元件標記 39
4.4 硬體加速器實作 40
4.4.1 前景分割加速器實作 40
4.4.2 斷開法加速器實作 41
4.4.3 連通元件標記加速器實作 43
4.5 軟硬體系統架構 45
4.6 介面控制器設計 46
4.7 硬體模組驗證 47
4.7.1 前景分割模組驗證 47
4.7.2 侵蝕模組驗證 49
4.7.3 色彩轉換模組 49
4.7.4 硬體模組間管線化設計比較 50
第五章 結論與未來研究方向 53
5.1 結論 53
5.2 未來研究方向 53
參考文獻 55
附錄1 59
附錄2 60
附錄3 61
附錄4 63
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指導教授 陳慶瀚(Cing-hang Chen) 審核日期 2014-7-11
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