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姓名	廖柏翔(Po-Hsiang Liao)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	鍺奈米球/二氧化矽/矽鍺殼異質結構之應力工程與無接面N型金氧半場效電晶體研製 (Strain engineering on Ge-nanosphere/SiO2/Si1-xGex-shell heterostructure and junctionless n-MOSFETs)
相關論文	★ 量身訂作鍺量子點崁入式發射器與鍺量子點光偵測器應用於單石積體化矽光電晶片
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摘要(中)	為了提高電晶體的特性以增進人類福祉，更換電晶體之通道材料已經勢在必行。在所有可能的材料中鍺因為具有較矽通道更高的電子電洞遷移率而備受矚目，更重要的是鍺材料與現今互補式金屬氧化物半導體製程相容。然而要實現鍺金氧半元件之難度在於將低缺陷密度之高品質鍺沉積在矽上，以及在鍺材料上形成令人滿意的界面與電特性之閘介電層，此兩種對鍺元件來說相當具有挑戰性。此外，摻雜活化效率低、摻雜擴散快以及費米能接釘住之問題，更讓N型鍺通道電晶體較P型鍺通道電晶體更難實現。我們研究團隊過去已利用單一步驟氧化的方式，成功在矽基板上製作出獨特的自聚式鍺奈米球/二氧化矽/矽鍺奈米片異質結構。基於這樣的結構，本文提出局部高濃度矽鍺奈米片之結構，以達到高性能矽鍺甚至是純鍺之N型金氧半場效電晶體之應用。 　　為了製作鍺奈米球/二氧化矽/矽鍺奈米片金氧半場效電晶體，本文討論了矽鍺柱氧化完後之二氧化矽與鍺奈米球/二氧化矽/矽鍺奈米片之幾何結構尺寸調控。尺寸調控0.75%–3.2%的伸張式應力與0.7%–4.5%的壓縮式應力，已分別在鍺奈米晶粒包覆在二氧化矽與氮化矽的結構中得到驗證。在伸張式或壓縮式應力下，鍺量子點之晶格畸變也藉由量測格留乃森参数、非和諧參數與選區繞射圖得到驗證。介入氧化層厚度2.5奈米至4.5奈米與矽鍺奈米片厚度2.3奈米至22.5奈米，已藉由鍺奈米球鑽入矽基板之厚度所調控。此外，矽鍺片之晶格方向似乎沿襲著一開始矽基板晶格方向來成長。鍺濃度為85%、壓縮式應力為3%之單晶(100)矽鍺通道也成功地被驗證。另外，鍺濃度為35%、壓縮式應力為1.5%之單晶(110)矽鍺通道也成可成功地被製作出來。 　　結合以上的技術，本文已利用自聚式鍺奈米球/二氧化矽/矽鍺奈米片異質結構，成功地在(100)面絕緣體上的矽層中，製造並量測出鍺含量為85%之矽鍺無界面N型電晶體。我們的鍺奈米球/二氧化矽/矽鍺奈米片閘堆疊結構，在閘介電層沉積之前或之後，無須進行表面處理後額外的回火。在通道長度為75奈米，溫度為80K下給定閘極偏壓+1V、汲極偏壓+1V，量測到次臨限斜率為150mV/dec與開關路電流比大於5×108，顯示此元件具有優越的閘控制能力。計算所得之載子遷移率高達312.84cm2/V·s。最後，本文中也討論了源/汲極電阻、外在與固有之轉導、及轉導效率等進一步的元件特性。
摘要(英)	To boost the performance of the transistor for improving the human’s life, change the channel material is imperative definitely. Among the possible materials for the replacement of the Si channel, Ge is particularly attractive due to the high mobility for both electrons and holes. Most importantly Ge is compatible with the current CMOS technology. However, the challenge for the realization of the Ge MOS devices lies in the growth of high-quality Ge on Si with sufficiently low defect densities as well as the formation of gate dielectric on Ge with satisfactory interfacial and electrical properties, both of which are incredibly challenging. Furthermore, the low dopant activation efficiency, high dopant diffusivity, and the Fermi-level pinning lead to the realization for the Ge n-MOSFET is much more difficult than Ge p-MOSFET. Our group had successfully demonstrated unique self-assembly, gate-stack heterostructure of Ge nanosphere/SiO2/Si1-xGex nanosheet on the top of Si substrate using a one-step oxidation process. Base on this result, this thesis purpose a local, high Ge contents Si1-xGex nanosheet structure to achieve the high-performance Si1-xGex n-MOSFET. 　　In order to fabricate the Ge nanosphere/SiO2/Si1-xGex nanosheet MOSFET, this thesis has discussed the geometrical size control for the growing oxide formed by Si1-yGey nano-pillar oxidation, and the tunability for the heterostructure of Ge nanosphere/SiO2/Si1-xGex. Size-tunable strain engineering for the tensile strains of 0.75%–3.2% and compressive strain of 0.7%–4.5% have been demonstrated for the Ge nanocrystals embedded within the SiO2 and Si3N4 respectively. The crystalline distortions are observed in both strain states as evidenced by measurements of the Grüneisen parameters, anharmonic parameters, and lattice spacings through the selective area diffraction patterns. The intervening SiO2 thickness of 2.5nm–4.5nm and Si1-xGex nanosheet thickness of 2.3nm–22.5nm are successfully tailored by the penetration depth of the Ge nanosphere within the Si substrate. Furthermore, the crystalline orientation of the Si1-xGex nanosheet appears to inherit the original crystal orientation of these Si layers. Single-crystalline (100) Si1-xGex channels with Ge content as high as x = 0.85 and a compressive strain of 3% were successfully demonstrated. Additionally, (110) Si1-xGex channels with Ge content as high as x = 0.35 with a corresponding compressive strain of 1.5% were shown to be feasible. 　　Armed with these techniques, this thesis has successfully fabricated and characterized the Si0.15Ge0.85 junctionless n-MOSFETs comprising a gate-stacking heterostructure of Ge-nanospherical gate/SiO2/Si0.15Ge0.85-nanosheet on SOI (100) substrate in a self-organization approach. No surface treatments before the gate-dielectrics deposition nor additional processes following gate-stack formation are needed for our Ge nanosphere/SiO2/Si1-xGex nanosheet gate-stacking structure. Superior gate modulation is evidenced by subthreshold slope of 150mV/dec and ION/IOFF > 5×108 (IOFF < 10-6 uA/um and ION > 500 uA/um) measured at VG = +1V, VD = +1V, and T = 80K for our device with channel length of 75nm. The calculated mobility reaches as high as 312.84 cm2/V·s. Device detail properties such as S/D resistance, extrinsic and intrinsic transconductance, as well as transconductance efficiency are also discussed in this thesis.
關鍵字(中)	★ 應力工程 ★ 鍺閘極 ★ 矽鍺奈米薄層 ★ 無接面場效電晶體 ★ 自聚	關鍵字(英)	★ Strain engineering ★ Ge gate ★ SiGe nanosheet ★ junctionless FET ★ self organization
論文目次	摘要 i Abstract iii 誌謝 v Table of contents viii List of figures xi List of tables xxiv Chapter 1 Introduction 1 1-1 Development of the transistor and IC 1 1-2 Possible solution for MOSFET scaling 2 1-2-1 Sub-thermionic transition and new device configurations 3 1-2-2 Alternative channel materials to improve the device performance 5 1-3 Challenges for Ge channel MOSFET 6 1-3-1 Heteroepitaxy of Ge on Si 6 1-3-2 Suitable gate dielectric for Ge channel devices 8 1-3-3 Development status for the Ge n- and p-MOSFET 10 1-4 Heterostructure of Ge nanosphere/SiO2/Si1-xGex nanosheet: New solution for the Ge MOSFET 11 1-5 Dissertation organization 15 Chapter 1 Reference 22 Chapter 2 Formation of self-organized Ge nanospherical gate/SiO2/SiGe shell-shaped nanosheet on Si substrate 31 2-1 Formation mechanism for the heterostructure of Ge NP/SiO2/Si1-xGex 32 2-2 Expansion for the growing SiO2 after Si1-yGey nano-pillar oxidation 34 2-3 Sample clean issues for the Ge substrate and growing oxide 37 2-3-1 Sample clean on Ge substrate 37 2-3-2 Sample clean on growing oxide 38 2-3-3 Conclusion in this section 39 Chapter 2 Reference 47 Chapter 3 Matrix strain engineering in Ge nanocrystals by embedding within SiO2 and Si3N4 49 3-1 Introduction for the Raman measurement 49 3-1-1 Principle for the Raman measurement 50 3-1-2 Raman phonon line shift and the meaning of Raman linewidth 51 3-2 Strain engineering for the Ge nanocrystals embedded within the SiO2. 54 3-3 Strain engineering for the Ge nanosphere embedded in Si3N4 56 3-4 Distortions of the diamond cubic lattice for the Ge NPs/NCs 58 3-5 Release for the compressive-strained Ge nanosphere 60 3-6 Strain engineering for the Ge NPs burrowing into the SOI substrate 61 3-7 Chapter summary 62 Chapter 3 Reference 70 Chapter 4 Gate-stack engineering and Si1-xGex channel properties for Ge MOS devices 75 4-1 Silicon interstitials effects to the Ge NP 75 4-2 Controllability for the depth of penetration of the Ge NP 77 4-3 The controllability for the thickness of intervening SiO2 layer 78 4-4 The thickness and properties for the single crystalline Si1-xGex shell 80 4-4-1 The thickness control for the single crystalline Si1-xGex shell 80 4-4-2 Crystal orientation for the Si1-xGex shell 81 4-4-3 Chemical composition and strain for the Si1-xGex shell 82 4-4-4 Crystallinity quality for the Si1-xGex shell 85 4-5 Chapter summary 86 Chapter 4 Reference 95 Chapter 5 Fabrication for self-organized Ge nanosphere/SiO2/Si1-xGex junctionless nMOSFET 97 5-1 Introduction 97 5-2 Si1-xGex JL nFET fabrication process flow and key process development 98 5-2-1 Development for the E-beam alignment 98 5-2-2 SF6 lateral etching test 101 5-3 Fabrication for the Si1-xGex JL nMOSFET 102 5-3-1 Film stacks and zero mask patterning 103 5-3-2 Si0.85Ge0.15 nano-pillar patterning and oxidation 104 5-3-3 Active area definition and implantation 106 5-3-4 Channel passivation and gate contact patterning 107 5-3-5 In situ n+ poly Si deposition, dopant annealing and gate patterning 109 5-3-6 Standard backend process 110 5-4 Process optimization and simplification 111 5-4-1 Process optimization 111 5-4-2 Process simplification 112 Chapter 5 Reference 126 Chapter 6 Electrical characteristics for the Si1-xGex junctionless MOSFET 127 6-1 Introduction 127 6-2 Electrical characteristics for the Si0.15Ge0.85 channel JL MOSFET 129 6-3 Resistance, gm efficiency, mobility, and optical property for the Si0.15Ge0.85 channel JL MOSFET 131 6-3-1 gm efficiency for the Si0.15Ge0.85 channel JL MOSFET 132 6-3-2 Resistance for the Si0.15Ge0.85 channel JL MOSFET 132 6-3-3 Intrinsic transconductance (gm,int) and effective mobility (mFE) 134 6-3-4 Optical property for the Si0.15Ge0.85 channel JL MOSFET 135 6-4 Peeling and disappear for the Ge NP gate after several times electrical stress 135 6-5 Chapter summary 135 Chapter 6 Reference 143 Chapter 7 Conclusion and future work 146 7-1 Conclusion 146 7-2 Future work 148 Chapter 7 Reference 153 Appendix A. Global alignment ability in ELS7500 at National Nano Device Laboratories (NDL) A
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指導教授	李佩雯 郭明庭(Pei-Wen Li Ming-Ting Kuo)	審核日期	2019-1-22
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