具頻寬校正機制之寬頻三倍頻鎖相迴路設計

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姓名

徐延慶(Yen-Ching Hsu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具頻寬校正機制之寬頻三倍頻鎖相迴路設計
(A Wide Range Triple-Push Phase-Locked Loop with Bandwidth Calibration)

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摘要(中)

本論文提出一個可操作在0.8 GHz ~ 8.1 GHz，並具有頻寬校正機制之寬頻操作鎖相迴路。藉由三推式倍頻技術，將多相位振盪器輸出進行諧波混波後產生三倍頻，此三倍頻器是獨立於鎖相迴路之外，因此不會影響原鎖相迴路迴授系統，但又能擴增三倍的頻率輸出，因此能減緩寬範圍操作所帶來的鎖相迴路迴路頻寬設計困難度。其中在振盪器與三倍頻器的部分使用差動式的電路架構來強化三次諧波能量，並透過外部控制碼來供使用者選擇鎖相迴路輸出頻率，以同一組控制碼調整電荷幫浦之電流以確保迴路穩定性，達到頻寬校正之機制。此外利用高匹配度的電路佈局方式取代其他相位平均的電路技術，不僅可以有效減少多相位訊號之間的不匹配，也不會增加額外的硬體面積與功率消耗。

本論文之寬頻操作鎖相迴路使用90 nm CMOS製程實現晶片，供應電壓為1 V，鎖相迴路輸出時脈為0.8 GHz ~ 2.7 GHz，而三倍頻器輸出時脈為2.4 GHz ~ 8.1 GHz，所有頻率的方均根抖動(JitterRMS)表現皆小於5%時脈週期，在頻寬效正的部分，在1 MHz位置的相位雜訊最大的改善量為10 dBc/Hz，此時的輸出頻率為2.7 GHz。整體晶片所佔面積為1.20 mm2，電路所佔面積為0.048 mm2，電路操作在最高頻率時的功率消耗為13.9 mW。

摘要(英)

A 0.8 ~ 8.1 GHz wide range phase-locked loop (WRPLL) with bandwidth calibration mechanism is proposed. In this thesis, triple-push technique is used to extend the oscillator tuning range without influence the stability of phase-locked loop. Furthermore, it can relieve difficulties effectively in design loop bandwidth for wide range application. For the weakness of the tripler output power, differential structure are used in oscillator and tripler to enhance 3rd harmonic energy. The output swing of tripler is about twice as large as the traditional single-ended structure. The off-chip control signals are used to adjust both divider ratio and charge pump current in order to maintain the bandwidth and stability across the operating range. In a addition, instead of using any other phase averaging techniques, this thesis proposed a highly symmetric layout method to reduce phases mismatch without increase extra area cost.

The experiment chip of the proposed WRPLL was implemented with 90 nm CMOS process. The measured output frequency is 0.8 ~ 2.7 GHz for PLL output and 2.4 ~ 8.1 GHz for tripler output at 1.0 V supply voltage with 13.9 mW power consumption at the highest operating frequency. The maximum improvement of phase noise after bandwidth calibration is 10 dBc/Hz at 1 MHz frequency offset at 2.7 GHz output frequency. The full chip area is 1.20 mm2 and the core area is 0.048 mm2.

關鍵字(中)

★ 三倍頻
★ 頻寬校正
★ 寬頻鎖相迴路

關鍵字(英)

★ Triple-Push
★ Bandwidth Calibration
★ Wide Range PLL

論文目次

摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 viii
表目錄 xii
第一章緒論 1
1.1 研究動機 1
1.2 論文架構 2
第二章寬頻操作鎖相迴路先前技術探討 5
2.1 鎖相迴路簡介與系統分析 5
2.2 寬頻操作鎖相迴路簡介 12
2.2.1 頻寬校正機制 13
2.2.1.1 調整參考頻率之頻寬校正方法 14
2.2.1.2 調整除數之頻寬校正方法 15
2.3 寬頻操作鎖相迴路先前技術探討與面臨到的問題 16
2.3.1 使用自我偏壓技術之抗製程變異鎖相迴路[5] 16
2.3.2 具數位式自我頻寬校正之鎖相迴路[7] 17
2.3.3 全數位式寬頻操作鎖相迴路[10] 19
2.3.4 寬範圍操作之三推式環形振盪器[8] 21
2.3.5 高輸出能量之三推式環形振盪器[9] 23
2.3.6 延遲鎖定迴路為基礎之頻率合成器[11] 24
2.4 本論文之寬頻鎖相迴路預計規格 25
第三章具三推式倍頻技術之寬頻操作鎖相迴路 27
3.1 設計概念 27
3.2 電路架構與操作 27
3.2.1 三推式壓控振盪器之操作 28
3.2.2 頻寬控制器之操作 31
3.3 行為模擬 35
第四章子電路架構設計考量與模擬 39
4.1 寬頻操作鎖相迴路之子電路設計 39
4.1.1 相位頻率偵測器 39
4.1.2 電荷幫浦 41
4.1.3 迴路濾波器 43
4.1.4 電壓控制振盪器 43
4.1.5 多模數除頻器 46
4.2 差動式三倍頻器之電路設計 48
4.3 頻寬控制器之電路設計 50
4.4 電壓控制振盪器之佈局考量 52
第五章電路模擬與晶片量測結果 57
5.1 設計流程 57
5.2 佈局後電路模擬 58
5.2.1 寬頻操作鎖相迴路 58
5.2.2 差動式三倍頻器 60
5.3 電路佈局 62
5.4 晶片照相與量測環境設定 66
5.5 晶片量測結果 71
5.5.1 寬頻操作鎖相迴路量測結果 72
5.5.2 差動式三倍頻器量測結果 75
5.5.3 頻寬校正機制量測結果 79
5.6 規格比較 82
第六章結論與未來研究方向 85
6.1 結論 85
6.2 未來研究方向 86
參考文獻 87

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2016-7-25

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