具溫度及電壓變異補償技術之 非石英式時脈產生器

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：32

、訪客IP：18.223.239.250

姓名

葉家齊(Chia-Chi Yeh) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具溫度及電壓變異補償技術之非石英式時脈產生器
(Crystal-less Clock Generator with Temperature and Supply Voltage Compensation)

相關論文

★ 一種應用於觸控液晶顯示器的新型嵌入式開關	★ 多重相位之延遲鎖定迴路倍頻器設計與分析
★ 2.5Gbps串列收發器設計	★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路	★ 全數位任意責任週期之同步映射延遲電路
★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測	★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統
★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路	★ 高解析度可變動責任週期之同步複製延遲電路
★ 奈米CMOS晶片內序列傳輸之接收器	★ 奈米CMOS晶片內序列傳輸之送器
★ 基於鎖相迴路之多重相位脈波產生器	★ 低能量時脈儲存元件之分析、設計與量測
★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器	★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

本論文提出具溫度對頻率補償機制之非石英式時脈產生器，針對低頻及高頻應用的不同需求，共提出兩種電路架構。第一種為8 MHz非石英式時脈產生器，將傳統弛張振盪器的架構進行改良，對於供應電壓源以及溫度漂移有較佳的抵抗能力，並在脈波產生器對迴路延遲時間做溫度補償。在晶片溫度漂移為-40 °C至150 °C的範圍內，量測到的輸出頻率變異量最佳值為10.9 ppm/ °C。在供應電源漂移為±10 %的範圍內，量測到的輸出頻率變異量小於0.28 %。第二種為具十六相位輸出之768 MHz非石英式時脈產生器，架構中環型振盪器的供應電源來自輸出電壓溫度係數為正的穩壓器，可以補償電晶體之載子遷移率對於輸出頻率的負溫度效應，並在環型振盪器中加入溫度補償係數之微調電路，使輸出頻率在不同的製程漂移下都能達到最佳的溫度補償效果。其操作頻率為768 MHz時，溫度漂移為 -40 °C至150 °C的範圍內，量測到的輸出頻率變異量最佳值為110.7 ppm/ °C。在供應電源漂移為±10 %的範圍內，量測到的輸出頻率變異量小於0.96 %。故本論文設計之非石英時脈產生器可以在系統因硬體面積受限而無法使用石英振盪器時，提供可靠之穩定時脈，當作時脈倍頻器的參考訊號，或是取代整個時脈倍頻器加上傳統石英振盪器的組合，達到較小面積和低成本的設計。

摘要(英)

Two on-chip crystal-less clock generator (CLCG) with temperature compensation are presented. For both high speed and low speed applications, this thesis contain two kinds of architectures. The first one is a 8 MHz relaxation oscillator. The voltage and current reference circuits have high immunities of temperature and supply voltage variations. A proposed pulse generator is used to eliminate the loop delay time variation caused by temperature drift. Under the temperature range is form -40 °C to 150 °C, the measured output frequency accuracy is 10.9 ppm/°C. Under the ±10 % supply voltage, the output frequency variations is less than 0.28%. The second architecture is a 768 MHz multi-phase clock generator with temperature compensation. The supply voltage of the multi-phase ring oscillator is from a regulator which has positive temperature coefficient that can compensate the output frequency drift caused by temperature variation. Besides, we apply a temperature coefficient calibration circuit to make sure the output frequency has higher accuracy in the process variations. The output frequency accuracy of 768 MHz is 110.7 ppm/°C, under the temperature range is form -40 °C to 150 °C. In some applications limited by hardware area, traditional crystal oscillator can be replaced with these crystal-less clock generator, and it would consume less cost and area.

關鍵字(中)

★ 非石英式時脈產生器
★ 溫度補償
★ 電壓補償

關鍵字(英)

★ crystal-less clock generator
★ temperature compensation
★ voltage compensation

論文目次

摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 vi
表目錄 viii
第一章緒論 1
1.1 研究動機 1
1.2 研究目的及其應用 1
1.3 論文架構 3
第二章非石英式時脈產生器 4
2.1 非石英式時脈產生器種類簡介 4
2.2 非石英式時脈產生器架構探討 6
2.2.1 溫度補償之弛張振盪器6[10][11] 6
2.2.2 含溫度補償之非石英振盪器[5] 9
2.2.3 具電感電容振盪器之非石英振盪器[7] 10
2.2.4 應用於生醫系統具頻率追鎖迴路之非石英振盪器[8] 11
2.2.5 非石英式時脈產生器架構規格比較 12
2.3 本論文預期規格 13
第三章具溫度補償技術之弛張振盪器 15
3.1 研究動機 15
3.2 電路架構 15
3.2.1 電路設計原理 15
3.2.2 帶差參考電路 17
3.2.3 低溫度係數之參考電流源 22
3.2.4 比較器及脈波產生器 24
3.3 實作結果 27
3.3.1 設計流程 27
3.3.2 電路模擬 27
3.3.3 電路佈局 30
3.3.4 晶片照相圖與量測環境設定 31
3.3.5 量測結果 33
3.3.6 規格比較 38
第四章具溫度補償機制之多相位非石英振盪器 39
4.1 研究動機 39
4.2 電路架構 39
4.2.1 電路設計原理 39
4.2.2 正溫度係數參考電壓源 43
4.2.3 穩壓器 44
4.2.4 具十六相位輸出之環形振盪器及溫度係數微調電路 46
4.3 實作結果 50
4.3.1 電路模擬 50
4.3.2 電路佈局 52
4.3.3 晶片照相圖與量測環境設定 54
4.3.4 量測結果 56
4.3.5 規格比較 61
第五章結論與未來研究方向 62
5.1 結論 62
5.2 未來研究方向 63
參考資料 64

參考文獻

[1] Y. Tokunaga, S. Sakiyama, A. Matsumoto, and S. Dosho, “An on-chip CMOS relaxation oscillator with voltage averaging feedback”, IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1150-1158, Jun. 2010.

[2] U. Denier, “Analysis and design of an ultralow-power CMOS relaxation oscillator”, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 8, pp. 1973-1982, Aug. 2010.

[3] http://www.aecouncil.com/AECDocuments.html

[4] Y. Lu, G. Yuan, L. Der, W.-H. Ki, and C. P. Yue, “A ±0.5 % precision on-chip frequency reference with programmable switch array for crystal-less applications” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 10, pp. 642-646, Oct. 2013.

[5] F. Sebastiano, L. J. Breems, K. Makinwa, S. Drago, D. Leenaerts, and B. Nauta, “A 65-nm CMOS temperature-compensated mobility-based frequency reference for wireless sensor networks” , IEEE J. Solid-State Circuit, vol.46, no.7, pp.1544-1552, Jul. 2011.

[6] F. Sebastiano, L. Breems, K. Makinwa, S. Drago, D. Leenaerts, and B. Nauta, “A low-voltage mobility-based frequency reference for crystal-less ULP radios,” IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 2002-2009, July. 2009.

[7] M. S. McCorquodale, J. D. O′ Day, S. M. Pernia, G. A. Carichner, S. Kubba, and R. B. Brown, "A monolithic and self-referenced RF LC clock generator compliant with USB 2.0," IEEE J. Solid-State Circuits, vol. 42, no.2, pp. 385-399, Feb. 2007.

[8] W.-H. Sung, S.-Y. Hsu, J.-Y. Yu, C.-Y. Yu, and C.-Y. Lee, “A frequency accuracy enhanced sub-10uW on-chip clock generator for energy efficient crystal-less wireless biotelemetry applications,” in Proc. IEEE Symp. On VLSI, 2010, pp. 115-116.

[9] J.-C. Liu, W.-C. Lee, H.-Y. Huang, K.-H. Cheng, C.-J. Huang, Y.-W. Liang, J.-H. Peng, and Y.-H. Chu, “A 0.3-V all digital crystal-less clock generator for energy harvester applications,” in Proc. Asian Solid-State Circuits Conference, 2012, pp.117-120.
[10] Y.-H. Chiang, and S.-I. Liu, “A submicrowatts 1.1 MHz CMOS relaxation oscillator with temperature compensation,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 12, pp. 837-841, Dec. 2013.

[11] Y.-H. Chiang, and S.-I. Liu, “Nanopower CMOS relaxation oscillator with sub-100 ppm/°C temperature coefficient,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 9, pp. 661-665, Jun. 2014.

[12] K. Sundaresan, “Process and temperature compensation in a 7-MHz CMOS clock oscillator,” IEEE J. Solid-State Circuits, vol. 41, no.2, pp. 433-442, Feb. 2006.

[13] Behzad Razavi, “Design of analog CMOS integrated circuits,” 2005.

[14] 張啟揚, “操作在0.5伏特下具溫度補償技術非石英振盪器之全數位式時脈產生器,” 碩士論文, 國立中央大學, 2013.

[15] N. Sadeghi, A. Sharif-Bakhtiar, and S. Mirabbasi, “A 0.007-mm2 108-ppm/°C 1-MHz relaxation oscillator for high-temperature application up to 108 °C in 0.13-μm CMOS,” IEEE Trans. Circuits Syst. I, Regular Papers, vol. 60, no. 7, pp. 1692-1701, Jun. 2013.

[16] J. Lee, and S.-H. Cho, “A 1.4-µW 24.9-ppm/°C current reference with process-insensitive temperature compensation in 0.18-µm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no.10, pp. 2527-2533, Jul. 2012.

[17] Y. Zhang, W. Rhee, T. Kim, and H. Park, “A 0.35-0.5-V 18-152 MHz digitally controlled relaxation oscillator with adaptive threshold calibration in 65-nm CMOS
[18] ,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 62, no. 8, pp. 736-740, Jun. 2015.

[19] K.-K. Huang, and D. D. Wentzloff, “A 1.2-MHz 5.8-μW temperature compensated relaxation oscillator in 130-nm CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 5, pp. 334-338, Apr. 2014.

[20] K.-J. Hsiao, “A 32.4 ppm/°C 3.2-1.6 V self-chopped relaxation oscillator with adaptive supply generation,” IEEE Symp. On VLSI, 2012, pp. 14-15.

[21] T. Tokairin, K. nose, K. Takeda, and K. Noguchi, “A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feed-forward period control scheme,” IEEE Symp. On VLSI, 2012, pp. 16-17.

[22] S. M. Kashmiri, M. A. P. Pertijs, and K. A. A. Makinwa, “A thermal-diffusivity-based frequency reference in standard CMOS with an absolute inaccuracy of ±0.1 % from - 55 °C to 125 °C,” IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 2510-2520, Dec. 2010.

[23] Y. Cao, P. Leroux, W. De Cock, and M. Steyaert, “A 63,000 Q-factor relaxation oscillator with switched-capacitor integrated error feedback,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2013, pp. 402-403.

[24] A. Paidimarri, D. Griffith, A. Wang, and A. P. Chandrakasan, “A 120nW 18.5kHz RC oscillator with comparator offset cancellation for ±0.25 % temperature stability,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 184-185, Feb. 2013.

[25] K. Sundaresan, P. E. Allen, and F. Ayazi, “Process and temperature compensation in a 7-MHz CMOS clock oscillator,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 433-442, Feb. 2006.

[26] J. Lee, and S.-H. Cho, “A 10MHz 80μW 67 ppm/°C CMOS reference clock oscillator with a temperature compensated feedback loop in 0.18μm CMOS,” IEEE Symp. On VLSI, 2009, pp. 226-227.

[27] C.-C. Chung, and C.-R. Yang, “An autocalibrated all-digital temperature sensor for On-Chip thermal monitoring,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no.2, pp. 105-109, Feb. 2011.

[28] K.-H. Cheng, J.-C. Liu, and H.-Y. Huang, “A 0.6-V 800-MHz all-digital phase-locked loop with a digital supply regulator,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 12, pp. 888-892, Jan. 2013.

[29] Y.-C. Shih, and B. Otis, “An on-chip tunable frequency generator for crystal-less low-power WBAN radio,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 4, pp. 187-191, Mar. 2013.

[30] K. Ueno, T. Hirose, T. Asai, and Y. Amemiya, “A 300 nW, 15 ppm/°C, 20 ppm/V CMOS voltage reference circuit consisting of subthreshold MOSFETs,” IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 2047-2054, Feb. 2009.

[31] R. Vijayaraghavan, S. K. Islam, M. R. Haider, and L. Zuo, “Wideband injection-locked frequency divider based on a process and temperature compensated ring oscillator,” IET Circuits, Devices & Systens, vol. 3, no. 5, pp. 259-267, Oct. 2009.

[32] X. Zhang, and A. B. Apsel, “A low-power, process and temperature compensated ring oscillator with addition-based current source,” IEEE Trans. Circuits Syst. I, Regular Papers, vol. 58, no. 5, pp. 868-878, Jun. 2010.

[33] G. Wu, K. Sun, S. Guo, and T. Zhang, “A low-voltage and temperature compensated ring VCO design,” IEEE Dallas Circuits and Systems Conf., 2014, pp. 1-4.

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2016-7-25

推文