適用於生理訊號檢測之低功耗連續時間三角積分調變器

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姓名

楊仁傑(Ren-Chien Yang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用於生理訊號檢測之低功耗連續時間三角積分調變器
(A Design of Low Power Continuous Time Delta-Sigma Modulator for Biosignal Applications)

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摘要(中)

隨著老年化時代的來臨以及各種文明病的出現，現代人越來越注重自己的身體監控，各種穿戴式血壓血糖心跳感測器應運而生。由於穿戴式的感測器通常需長時間的配戴，因此輕巧及省電為主要考量。一般生理訊號量測系統可分為感測與後端處理，而後端處理可藉由積體電路實現進而縮小整體系統面積。
本論文為設計一個適用於生理訊號量測的類比數位轉換器(Analog to Digital Converter, ADC)，使用連續時間三角積分調變器(Continuous Time Delta-Sigma Modulator, CTDSM)實現，架構為三階積分器與一位元量化器。此ADC能處理常見的生理訊號並具有足夠的解析度，完整地將前端低雜訊放大器處理過後的訊號轉換為數位資料。另外CTDSM具有隱性抗交疊濾波器(Anti-Aliasing Filter, AAF)的特性，在系統上可以省去或減緩前級AAF的使用進而省下一些功耗。在相同積分電容下，比起離散時間，連續時間積分器可以使用較小功耗達到規格要求。而一位元量化器擁有最好的線性度並可降低電路的複雜度。
本次晶片實現使用台積電0.18 um CMOS 1P6M製程，晶片大小為0.8483 mm2。在頻寬為10 KHz下，其輸入動態範圍為88 dB、有效解析度位元(ENOB)為12.6 bits、超取樣率為64。在1.8 V電源供應下，整體晶片功耗為140 uW。

摘要(英)

With the coming of aging societies and the emergence of civilized illness, modern people increasingly focus on their body monitoring, so that various wearable devices of blood pressure, blood glucose and heart rate sensors have been launched. However, it usually be worn for long periods of time, so the lightweight and higher power efficiency are the key factors in considering. In general, biosignal detection system can be classified as sensor and the back-end processing circuit. The back-end processing circuit may be implemented by the integrated circuit (IC) to minimize the area.
This thesis designs an analog to digital converter (ADC) for biosignal applications and implemented by continuous time delta-sigma modulator (CTDSM). The structure of the modulator is a third-order integrator and single bit quantizer. This ADC could process common biosignals and has enough resolutions to convert the analog signals to digital signals completely. In addition, the CTDSM also has the important property of implicit anti-aliasing filter (AAF), and it can relax the AAF front end and reduce power consumption in full system. Comparing to discrete time, the continuous time integrator can have lower power consumption to achieve the specification if both of them have the same type of integrator capacitor. In the end, the single bit quantizer can provide the best linearity and reduce the complexity of the circuit.
The chip was implemented in 0.18 um CMOS technology and the core size is 0.8483 mm2. This work achieves 86 dB dynamic range and 12.6 bits ENOB in 10 kHz signal bandwidth with an oversampling ratio of 64. The power consumption is 140 uW under 1.8 V supply voltage.

關鍵字(中)

★ 三角積分調變器
★ 類比數位轉換器
★ 抗交疊濾波器
★ 連續時間
★ 雜訊轉移函數
★ 訊號轉移函數

關鍵字(英)

★ Delta-Sigma Modulator (DSM)
★ Analog to Digital Converter (ADC)
★ Anti-aliasing Filter (AAF)
★ Continuous Time (CT)
★ Noise Transfer Function (NTF)
★ Signal Transfer Function (STF)

論文目次

摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 vi
表目錄 x
第一章緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文架構 3
第二章三角積分類比數位轉換器 5
2.1 基本原理 5
2.2 轉移函數 (Transfer Function) 6
2.3 離散-連續時間轉換 7
2.3.1 回授DAC之行為函數 7
2.3.2 脈衝響應不變(Impulse-invariant)等效轉換 8
2.3.3 隱性(Implicit)抗交疊濾波器 11
第三章系統模擬驗證 13
3.1 基本架構建立 13
3.1.1 量化雜訊 13
3.1.2 轉移函數與穩定度考量 16
3.1.3 積分器 23
3.1.4 離散-連續時間DSM轉換 28
3.2 非理想因素考量 32
3.2.1 雜訊 33
3.2.2 非理想積分器 37
3.2.3 迴路延遲 (Excess-Loop Delay) 40
3.2.4 時脈抖動 (Clock Jitter) 45
3.2.5 製程變異考量 50
第四章電路設計與模擬 55
4.1 系統電路 55
4.2 兩級全差動放大器(Two Stage Fully Differential Amplifier) 56
4.2.1 電路設計 58
4.2.2 共模回授電路(Common-Mode Feedback, CMFB) 61
4.2.3 運算放大器模擬結果 63
4.3 量化器與一位元數位類比轉換器 69
4.3.1 比較器 69
4.3.2 一位元數位類比轉換器 71
4.4 電壓產生參考電路 72
4.5 系統模擬結果 73
第五章晶片佈局與量測考量 75
5.1 晶片佈局 75
5.2 量測考量 77
5.2.1 輸入終端電路 78
5.2.2 產生供應電壓 78
5.3 文獻比較 79
第六章結論與未來展望 81
6.1 結論 81
6.2 未來展望 81
參考文獻 83

參考文獻

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指導教授

薛木添(Muh-Tian Shiue)

審核日期

2016-7-14

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