電阻性非揮發性靜態隨機存取式記憶體之測試與診斷

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姓名

李昱霆(Yu-Ting Li) 查詢紙本館藏

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電機工程學系

論文名稱

電阻性非揮發性靜態隨機存取式記憶體之測試與診斷
(Testing and Diagnosis of Memristor-Based Nonvolatile SRAMs)

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摘要(中)

在現今的系統晶片中，靜態功率消耗佔整個晶片功率消耗很大的部分。此外，靜態隨機存取式記憶體在晶片中時常超過整個晶片面積的一半以上。因此，在系統晶片中的靜態功率消耗主要會來自於靜態隨機存取式記憶體。非揮發性靜態隨機存取式記憶體在近年被提出，它能在電源關閉時保留住資料並且能在電源打開時快速的回復資料開來減少靜態隨機存取式記憶體在電源關閉時的靜態功率消耗。一個非揮發性靜態隨機存取式記憶體包含了靜態隨機存取式記憶體元件及非揮發性儲存元件。因此，測試非揮發性靜態隨機存取式記憶體會比測試靜態隨機存取式記憶體來的困難。

在這篇論文中，我們提出了應用於電阻性非揮發性靜態隨機存取式記憶體之測試及診斷技術。第一部分，我們在電阻性非揮發性靜態隨機存取式記憶體中定義了幾個憶阻器相關之錯誤。運用HSPICE來模擬及分析可能發生於電阻性非揮發性靜態隨機存取式記憶體之瑕疵。第二部分，我們針對電阻性非揮發性靜態隨機存取式記憶體之簡單靜態隨機存取式記憶體錯誤及憶阻器相關錯誤提出類行軍式測試及診斷演算法。為了要評估提出之演算法的錯誤涵蓋率，我們也實現了應用於電阻性非揮發性靜態隨機存取式記憶體之錯誤模擬器。在模擬的結果中，針對特定的錯誤所提出之測試及診斷演算法可以提供100%的錯誤涵蓋率及100%的診斷分辨率。最後，我們也實現了應用於電阻性非揮發性靜態隨機存取式記憶體之可產生類行軍式演算法的內建自我測試電路。根據模擬結果，針對一個256x8位元之非揮發性靜態隨機存取式記憶體，使用TSMC90奈米製程合成之可支援類行軍試演算法的自我測試電路約只需要642個邏輯閘。

摘要(英)

In modern system-on-chips (SOCs), static power consumption represents a significant portion of the chip power. Also, static random access memory (SRAM) typically occupies more than one half of the chip area. Therefore, the static power of a SOC is mainly constituted by the SRAMs. Nonvolatile SRAM has been proposed to preserve data in the power-down mode with the feature of fast power-on speed such that the static power of SRAM can be
eliminated in the power-down mode. A nonvolatile SRAM cell consists of a SRAM cell and a nonvolatile storage cell. Therefore, the testing of nonvolatile SRAM is much more difficult than that of SRAM.
In this thesis, we propose testing and diagnosis techniques for memristor-based (resistive) nonvolatile SRAMs. Firstly, several memristor-related faults of resistive nonvolatile SRAM are defined. Comprehensive defects are analyzed and simulated for the resistive nonvolatile 8-transistor SRAM using HSPICE. Secondly, we propose March-like test algorithms and diagnosis algorithms for covering simple SRAM faults and the defined memristor-related faults of resistive nonvolatile SRAMs. To evaluate the fault coverage of the proposed test algorithms, we also implement a fault simulator for nonvolatile SRAMs. Simulation and analysis results show that the proposed test and diagnosis algorithms can provide 100% fault coverage and 100% diagnostic resolutions for the targeted faults. Finally, a built-in
self-test design which can generate the March-like tests for resistive nonvolatile SRAMs is proposed. Simulation results show that only about 642 gates are needed to support March test algorithms for a 256×8-bit nonvolatile SRAM using TSMC 90nm standard cell library.

關鍵字(中)

★ 憶阻器
★ 非揮發性記憶體
★ 靜態隨機存取式記憶體
★ 錯誤模型
★ 測試演算法
★ 診斷演算法

關鍵字(英)

★ memristor
★ nonvolatile memory
★ SRAM
★ fault model
★ test algorithm
★ diagnosis algorithm

論文目次

1 Introduction 1
1.1 Memristors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Memristor-Based Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Nonvolatile SRAMs (nvSRAMs) . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Testing for SRAMs and Memristor-Based Memories . . . . . . . . . . . . . . 5
1.4.1 Functional Faults of Typical 6T-SRAMs . . . . . . . . . . . . . . . . 5
1.4.2 March-Like Test and Diagnosis of SRAMs . . . . . . . . . . . . . . . 6
1.4.3 Testing of Memristor-Based Memories . . . . . . . . . . . . . . . . . 7
1.5 Built-In Self-Test Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.6 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Fault Modeling for Memristor based nvSRAMs 10
2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Functional Fault Modeling of nvSRAMs . . . . . . . . . . . . . . . . . . . . 11
2.3 Case Study Memristor-related Faults . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1 Rnv8T SRAM Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.2 Electrical Defects and Simulation Model . . . . . . . . . . . . . . . . 16
2.3.3 Electrical Fault Models of Rnv8T SRAMs . . . . . . . . . . . . . . . 19
2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3 Testing and Diagnosis for nvSRAMs 26
3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2 Test Requirement for Nonvolatile SRAM . . . . . . . . . . . . . . . . . . . . 26
3.3 Test Algorithm for nvSRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.1 March CM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.2 March MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4 Diagnosis Algorithm for nvSRAMs . . . . . . . . . . . . . . . . . . . . . . . 30
3.4.1 Two-Phase Diagnosis Algorithm . . . . . . . . . . . . . . . . . . . . . 30
3.4.2 March CMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5 Fault Simulator for nvSRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5.1 Existing Fault Simulator . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5.2 nvSRAM Fault Simulator . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6 Simulation and Analysis Results . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4 Built-In Self-Test Design for nvSRAMs 45
4.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2 Existing Programmable Built-In Self-Test Schemes . . . . . . . . . . . . . . 45
4.3 Built-In Self-Test Design for nvSRAMs . . . . . . . . . . . . . . . . . . . . . 46
4.4 Simulation Results and Comparison . . . . . . . . . . . . . . . . . . . . . . . 50
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5 Conclusion and Future Work 52
5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

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指導教授

李進福(Jin-Fu Li)

審核日期

2016-12-29

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