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姓名	羅時慶(Shih-cing Luo)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	調變不同矽與氧流量及氧化溫度所製作鍺奈米球/二氧化矽/ 矽鍺異質結構 (Optimization of silicon and oxygen flux and oxidation temperature on Ge-nanoball/SiO2/SiGe gate-stacking heterostructure)
相關論文	★ 高效能矽鍺互補型電晶體之研製 ★ 高速低功率P型矽鍺金氧半電晶體之研究 ★ 應變型矽鍺通道金氧半電晶體之研製 ★ 金屬矽化物薄膜與矽/矽鍺界面反應 之研究 ★ 矽鍺異質源/汲極結構與pn二極體之研製 ★ 矽鍺/矽異質接面動態啓始電壓金氧半電晶體之研製 ★ 應用於單電子電晶體之矽/鍺量子點研製 ★ 矽鍺/矽異質接面動態臨界電壓電晶體及矽鍺源/汲極結構之研製 ★ 選擇性氧化複晶矽鍺形成鍺量子點的光特性與光二極體研製 ★ 選擇性氧化複晶矽鍺形成鍺量子點及其在金氧半浮點電容之應用 ★ 量子點的電子能階 ★ 鍺量子點共振穿隧二極體與電晶體之關鍵製程模組開發與元件特性 ★ 自對準矽奈米線金氧半場效電晶體之研製 ★ 鍺浮點記憶體之研製 ★ 利用選擇性氧化單晶矽鍺形成鍺量子點之物性及電性分析 ★ 應用於數位電視頻帶之平衡不平衡轉換器設計
檔案	[Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載] 本電子論文使用權限為同意立即開放。 已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。 請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。
摘要(中)	本論文藉由選擇性氧化複晶矽鍺奈米柱/氮化矽/矽材料的結構，來達到低成本、具自我對準且一體成形之鍺奈米球/二氧化矽/矽鍺合金之金氧半異質結構，並且以此結構做成矽鍺電晶體。之前本實驗室已驗證出此結構的介面缺陷約為3.5-5.5×1011 cm-2eV-1 ，足夠做為元件等級的介面，但目前本實驗室都是藉由濕氧900度來氧化矽鍺柱，形成4-5 nm的二氧化矽以及約10 nm的矽鍺合金層，對現今電晶體來說閘氧化層都已微縮至1 nm以下。所以想透過不同的氧化退火條件，來達到可以控制二氧化矽層的厚度，並且想利用SOI 基板使矽鍺合金層被二氧化矽限制住，讓矽鍺合金層的鍺濃度提升，進而增加矽鍺通道的載子遷移率。 我們做了一系列調變氧化退火條件的實驗，藉由調變氧化時氧流量、矽含量及氧化溫度進而找到最適合我們金氧半電容的條件。發現到當我們降低氧化退火溫度時，可以明顯看到閘介電層厚度有明顯下降的趨勢，且藉由電流-電壓、變頻電容-電壓量測可以看到不只厚度變薄，二氧化矽的品質跟著提升，對我們後續想做的矽鍺電晶體來說，無疑的是一種改善的方法。
摘要(英)	We demonstrated a unique approach to generate self-organized, self-alignment, and low-cost Ge-nanoball/SiO2/SiGe-shell gate-stacking heterostructures through the selective oxidation of poly-Si0.83Ge0.17 nano-pillars over the Si3N4 buffer layer on the Si substrate, and then would like to realize SiGe MOSFETs based on this designer heterostructure in the near future. It has been previously demonstrated that the interface trap density (Dit) of SiO2/SiGe heterostructure in the designer heterostructure is about 3.5−5.5 × 1011 cm-2eV-1, which is a promising candidate for high-performance Ge MOSFETs. However, 4nm-thick amorphous interfacial oxide layer was generated during thermal oxidation at 900 °C in H2O ambient, which cannot meet the criteria of prevailing CMOS technology with gate oxide less than 1 nm. In this work, we further reduced the thickness of this SiO2 interfacial layer by tuning the oxidation conditions, such as temperature and oxidation ambient. On the other hand, a SOI substrate was also employed to decrease the SiGe-shell thickness and then increase the Ge content in SiGe shell, forming a high-carrier mobility channel. According to a series of experiments with various oxygen fluxes and temperatures in thermal oxidation process as well as different Si substrate to control Si flux, we found the thickness of interfacial SiO2 layer would be significantly reduced with decreasing thermal oxidation/annealing temperature. Meanwhile, gate-oxide quality was also raised as the oxidation temperature decreased, which was confirmed by extensive current-voltage and capacitance-voltage characterizations in MOSC devices. Both results provide great promises for apply the designer gate-stacking heterostructure in Ge MOS applications.
關鍵字(中)		關鍵字(英)	★ Ge
論文目次	目 錄 中文摘要.....................................................................................................................................I 英文摘要....................................................................................................................................II 致 謝......................................................................................................................................IV 目 錄......................................................................................................................................VI 圖目錄....................................................................................................................................VIII 表目錄.....................................................................................................................................XII 第一章 簡介.............................................................................................................................1 1-1 前言.............................................................................................................................1 1-2 鍺通道電晶體所面臨之困難.....................................................................................3 1-3 研究動機……………………………………………………………….....................4 1-4 論文的整體架構.........................................................................................................5 第二章 鍺奈米球/二氧化矽/矽鍺異質堆疊結構形成機制..................................................8 2-1 前言.............................................................................................................................8 2-2 鍺奈米球/二氧化矽/矽鍺合金形成機制..................................................................8 2-3 改變氧化退火條件來控制金氧半異質結構............................................................9 第三章 鍺奈米球/二氧化矽/矽鍺異質堆疊結構形成機制與金氧半電容製作................21 3-1 前言...........................................................................................................................21 3-2 一體成形之鍺奈米球/二氧化矽/矽鍺異質堆疊結構優點....................................21 3-3 鍺奈米球電容製作流程………………………………………………………..….22 第四章 鍺奈米球電容元件的量測與分析...........................................................................32 4-1 前言...........................................................................................................................32 4-2 元件量測結果與分析...............................................................................................33 第五章 總結與未來展望.......................................................................................................40 參考文獻...................................................................................................................................41
參考文獻	參考文獻 [1] T. Ghani et al., “A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors,” IEDM Tech. Dig., p. 11.6.1, 2003. [2] D. Kuzum, “Interface-engineered Ge MOSFETs for future high performance CMOS applications,” dissertation for the degree of doctor, Stanford university, 2009. [3] D. Kuzum et al., “Ge Interface Engineering with Ozone Oxidation for Low Interface State Density,” IEEE Elec. Dev. Lett., vol. 29, p. 328, 2008. [4] P. Zimmerman, G. Nicholas, B. De Jaeger, B. Kaczer, A. Stesmans, L. A. Ragnarsson, D. P. Brunco, F. E. Leys, M. Caymax, G. Winderickx, K. Opsomer, M. Meuris, and M. M. Heyns, “High performance Ge pMOS devices using a Si-compatible process flow,” Tech. Dig. Int. Electron Devices Meets., 655 (2006). [5] Y. Nakakita, R. Nakane, T. Sasada, H. Matsubara, M. Takenaka, and S. Takagi, “Interface-controlled self-align source/drain Ge pMOSFETs using thermally-oxidized GeO2 interfacial layers,” Tech. Dig. Int. Electron Devices Meets., 877 (2008). [6] 楊國慶，“自組式鍺奈米球/二氧化矽/矽鍺合金閘堆疊異質結構之介面工程最佳化探討”，碩士論文，國立中央大學，民國103年。 [7] C. Y. Chien et al., “Nanoscale, catalytically enhanced local oxidation of silicon-containing layers by ‘burrowing’ Ge quantum dots,” Nanotechnology, vol. 22, p. 435602, 2011. [8] M. H. Kuo et al., “Designer Ge quantum dots on Si: A heterostructure configuration with enhanced optoelectronic performance,” Appl. Phys. Lett., vol. 101, p. 223107, 2012. [9] K. H. Chen, C. C. Wang, T. George, and P. W. Li “The pivotal role of SiO formation in the migration and Ostwald ripening of Ge quantum dots,” Appl. Phys. 105, 122102 (2014) [10] Nishimura T, Lee CH, Tabata T, Wang SK, Nagashio K, Kita K, et al. High-electronmobility Ge n-channel metal-oxide-semiconductor field-effect transistors with high-pressure oxidized Y2O3. Appl Phys Express. 2011;4:064201. [11] Zhang R, Iwasaki T, Taoka N, Takenaka M, Takagi S. High-mobility Ge pMOSFET with 1-nm EOT A2O3/GeOx/Ge gate stack fabricated by plasma post oxidation. IEEE Trans Electron Devices. 2012;59:335–41. [12] Lee CH, Nishimura T, Nagashio K, Kita K, Toriumi A. High-electron-mobility Ge/GeO2 n-MOSFETs with two-step oxidation. IEEE Trans Electron Devices. 2011;58:1295–301. [13] Takenaka M, Zhang R, Takagi S. MOS interface engineering for highmobility Ge CMOS. Proc IEEE Int Reliabil Phys Symposium. 2013;4C(1):1–8. Anaheim, 14–18 April.
指導教授	李佩雯、郭明庭(Pei-Wen Li Ming-Ting Kuo)	審核日期	2015-8-28
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