低功率損耗670伏超級接面金氧半場效電晶體元件之微縮設計

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姓名

鐘俊逸(Jyun-yi Jhong) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

低功率損耗670伏超級接面金氧半場效電晶體元件之微縮設計
(Device Scaling of 670V-class Super Junction MOSFETs with Low Power Loss)

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摘要(中)

超級接面金氧半場效電晶體(SJ MOSFET)關鍵技術在於精確地設計電荷平衡的元件結構。首先，我們分別模擬整理出未達電荷平衡時以及達成電荷平衡時，所對應之最大電場發生位置，以利於後續在模擬製程條件時，可以藉由調整N-epi的濃度、P-pillar寬度、P-pillar摻雜劑量等條件，來迅速達成電荷平衡的設計。綜合考量製程變異對於耐壓的變化(Process window)以及權衡兼顧崩潰電壓與導通電阻的優化，以下是我們經過多方模擬測試之後，針對主動區Cell pitch : 20m至14m元件的結構微縮所提出的設計法則：(1) WP = WN = CP/2；(2) Poly Gate Width = 0.7CP；(3) 保持總電荷相等 (WP × NP = WN × NN)。超級接面金氧半場效電晶體的結構設計，除了需優化主動區的元件之外，為了避免元件在周邊區域發生提早崩潰之情事，更需避免在周圍區域有大電場的聚集的情況發生。因此，我們提出使周圍區域的電場得以均勻分佈的方法：(1)以漸進梯度的方式來縮減周邊區域P型柱與柱間的距離；(2)周圍區域場板(Field plate)的長度優化設計。本論文利用Silvaco的Athena與Atlas，分別模擬製程流程與電性分析，並與實際元件，進行比對分析，確認優化設計之可行性。
總整模擬設計與實驗元件之測量結果可知，將元件Cell pitch從20m微縮至16m，雖然導致崩潰電壓從724降至678伏，但可以有效地調降特性導通電阻從3.4至2.45-mm2、也可調降閘極電荷(QG)從9.6至6.2nC，大幅降低功率損耗品質因子(FOM=Rdson×QG)約55%。模擬結果的趨勢與實驗結果吻合。為了進一步優化功率損耗品質因子，我們依Cell pitch=16m的條件為基準，藉由調變閘極寬從11m至9m，模擬結果顯示可再優化調降功率損耗品質因子約20%。根據此一模擬設計的元件結構，已有實際元件晶片產出，且驗證模擬設計法則之功效。

摘要(英)

The challenges for the production of SJ MOSFET lies in the exquisite design of charge-balancing. In this thesis, we systematically analyze the depth profile of E-field across p-pillars under various conditions including charge imbalance and charge balance. This allows us to gain insight on the E-field distribution, facilitating the design of p-pillar dosage, p-pillar width and n-epi concentration to achieve “charge balance” precisely and rapidly. Considering the process variations and following the charge balance principle, we have proposed a simple, effective design rule for downscaling the SJ MOSFETs with cell pitch of 1420m. The design rule is briefed as follows: (1) WP = WN = CP/2, (2) Poly Gate Width = 0.7CP, (3) achieving charge balance at the condition of WP × NP = WN × NN.
In addition to the device structure design in the cell, the structural design for the termination regions are also important in order to sustain high break down voltage for the entire system. We utilize two methods to make the E-field distribution as uniform as possible (to avoid the maximum E-filed occurring in specific regions). (1) A grading separation between pillar to pillar across the termination region, (2) Optimizing the field plate length design. We have used SILVACO Inc. Athena and Atlas simulator to simulate the device process and the corresponding electrical characteristics, respectively.
The effectiveness of simulation results has been verified by the experimental data from real devices based on our design. Decreasing the cell pitch from 20m to 16 m, experiment data demonstrate that, although the breakdown voltage declines from 724 to 678V, we are able to reduce the Ron,sp from 3.4 to 2.45 -mm2 and QG from 9.6 to 6.2nC simultaneously, effectively improving the FOM(Rdson×QG) approximately by 55%. For the further advancement of optimal FOM, we modulate the gate electrode width to reduce the gate charge. Simulation results show that decreasing gate electrode width from 11m to 9m, the FOM can be further improves by more than 20%.

關鍵字(中)

★ 超級接面
★ 功率金氧半場效電晶體

關鍵字(英)

★ Super junction
★ Power MOSFETs

論文目次

中文摘要 I
英文摘要 III
致謝 V
目錄 VI
圖目錄 VIII
表目錄 XIII
第一章 Power MOSFET的發展與研究動機 1
1-1 功率元件的發展 1
1-2 Power MOSFET的介紹 2
1-2-1 垂直式功率金氧半場效電晶體(VDMOSFET) 2
1-2-2 橫向式功率金氧半場效電晶體(LDMOSFET) 4
1-3 Power MOSFET崩潰機制 4
1-4 研究動機 6
1-5 論文概要 8
第二章超級接面金氧半場效電晶體的介紹與原理 14
2-1 超級接面概念由來 14
2-2 Super Junction MOSFET結構與原理 14
2-2-1 Super Junction的原理 14
2-2-2 Super Junction應用於Power MOSFET 15
2-3 超級接面結構的製作方式 17
2-3-1 多重磊晶成長法(Multi-step Epitaxial Growth) 17
2-3-2 溝槽填充法(Trench Filling) 18
第三章 670V SJ MOSFET微縮設計與製作流程 29
3-1 前言 29
3-2 既有元件之背景回顧 29
3-3 電荷平衡的分析 30
3-4 優化元件的柱狀結構 30
3-5 主動區的微縮設計 31
3-6 元件周邊耐壓區的設計 32
3-7 模擬SJ MOSFET製作完整流程 34
I. 製作超級接面結構 34
II. 形成場氧化層 34
III. 定義主動區並成長閘氧化層 34
IV. 成長複晶矽並定義閘極寬度 35
V. 形成P-body與N+源極區域 35
VI. 後段製程 35
第四章 670V SJ MOSFET模擬與實驗值的對照及分析 47
4-1實驗與模擬設計之直流特性驗證比較 47
4-1-1 模擬與實驗上P-pillar離子佈值劑量的差異 47
4-1-2 模擬與實驗上崩潰電壓的差異 50
4-1-3 元件的最後修正 51
4-2 實驗與模擬設計之動態特性比較 51
4-2-1 電容 (Capacitance) 51
4-2-2 閘極電荷(Gate Charge) 52
4-2-3 開關時間(Switching Time) 53
4-3 元件功率損耗分析 56
第五章結論與未來展望 72
參考文獻 73

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指導教授

李佩雯、郭明庭(Pei-Wen Li Ming-Ting Kuo)

審核日期

2015-8-19

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