||Recent years, long-term care or digital personal healthcare secretary is necessary. By improving the multi-purpose of biomedical instruments, reliability and reducing power consumption, equipment size and cost are conducive to today′s society. Therefore, this thesis will present a biomedical circuit design and describe how to achieve simplification, miniaturization, low power consumption, multi-purpose and high reliability. Finally hope this research will make everyone be better.|
This thesis consists of two parts, the first part introduces our research about biomedical analog front-end low-noise amplifier (LNA), which has operational bandwidth of 5 KHz, covering the EEG, ECG and other bio-signals. The CCIA architecture is used to block DC offset from electrode, taking the high impedance of Pseudo-Resistor to achieve miniaturization and extremely low frequency pole. Moreover, the current-reusing technique is used to maintain low power consumption and keep flicker noise and thermal noise to lower level. Behind the main block LNA, a programmable gain amplifier (PGA) is used. Hence not just only one bio-signal can be measured, but a variety of bio-signals measured can be applied.
In the second part, the successive approximation analog-to-digital converter (SAR ADC) is introduced which can meet the low-power consumption requirement. The function of SAR ADCs is converting the LNA analog signal to digital signal. The main idea of SAR ADCs is Monotonic Capacitor Switching Procedure which can effectively reduce energy loss to 19% of conventional architecture. On the other hand, by using monotonic switching procedure which can directly compare MSB, the overall capacitance array occupies only half of the conventional architecture, which can greatly reduce the chip area. The bootstrapped-switch is used to make input signal and sampling switch independent. The Ron of sampling switch will be fixed and make the S/H achieving high linearity. The main part of SAR ADCs is comparator. In this research the dynamic comparator is better for our research. Because the dynamic comparator only works in the conversion phase, by doing so the static power consumption can be saved. Our design achieves a 10-bit SAR ADC, the primary consideration of SAR ADCs design is low power requirement.
These circuits are designed in TSMC 0.18 μm CMOS 1P6M process. The first circuit is LNA, when input signal frequency is 250 Hz and 1 kHz, 500 μV input amplitude, the mid-band gain of analog front-end low-noise amplifier can be programmed from 35.917 dB to 53.979 dB. The post layout simulation shows that the input-referred noise is 1.811 μV rms, the Noise efﬁciency factor (NEF) is 1.39, the chip area (including ESD PAD) is 1.322 mm2, the overall chip consumes 2.19 μW. The second circuit is the SAR. When input signal frequency is 250 Hz and input amplitude 250mV, ENOB is 9.638 bits, SNDR is 60.1969 dB, the overall merit FOM is 0.55 pJ per conversion-step, the chip area (including ESD PAD) is 1.33 mm2, the overall chip consumes 2.602 μW.
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