高無失真動態範圍低功耗寬頻追蹤保持放大器之研製

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：5

、訪客IP：3.144.187.103

姓名

葉亞哲(Ya-che Yeh) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

高無失真動態範圍低功耗寬頻追蹤保持放大器之研製
(Design of High SFDR and Low Power Broadband Track-and-Hold Amplifiers)

相關論文

★ 微波及毫米波切換器及四相位壓控振盪器整合除三除頻器之研製	★ 微波低相位雜訊壓控振盪器之研製
★ 高線性度低功率金氧半場效電晶體射頻混波器應用於無線通訊系統	★ 砷化鎵高速電子遷移率之電晶體微波/毫米波放大器設計
★ 微波及毫米波行進波切換器之研製	★ 寬頻低功耗金氧半場效電晶體射頻環狀電阻性混頻器
★ 微波與毫米波相位陣列收發積體電路之研製	★ 24 GHz汽車防撞雷達收發積體電路之研製
★ 低功耗低相位雜訊差動及四相位單晶微波積體電路壓控振盪器之研究	★ 高功率高效率放大器與振盪器研製
★ 微波與毫米波寬頻主動式降頻器	★ 微波及毫米波注入式除頻器與振盪器暨射頻前端應用
★ 寬頻主動式半循環器與平衡器研製	★ 雙閘極元件模型與微波及毫米波分佈式寬頻放大器之研製
★ 銻化物異質接面場效電晶體之研製及其微波切換器應用	★ 微波毫米波寬頻振盪器與鎖相迴路之研製

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

本論文主要論述高無動態失真範圍低功耗寬頻追蹤保持放大器之研製，內容包含分佈式放大器與追蹤保持放大器兩部分。主要設計目標為寬頻、低功率消耗及高線性度。論文內容包含電路分析、理想原件電路模擬、整體電路模擬、電路佈局圖、量測結果與改進方法等。
分佈式放大器的部分主要會在第二章介紹。其設計原理包含分佈式放大器的基本組成、增加頻寬與高頻增益的方法和兩種負載的形式等。在章節中會有兩個晶片的實作，分別以改良主動式負載與電阻式負載兩種。設計的過程中會論述電晶體的偏壓與電晶體大小的選擇依據。在模擬方面先以理想元件進行初步評估，再來以佈局電路圖為依據，進行整體電路模擬。之後則是量測分析，量測參數主要以小訊號參數、增益1 dB壓縮點的輸出功率(P1dB)與三階擷取點輸出功率(OIP3)為主。在量測結果上，電阻式負載分佈式放大器頻寬約為DC-63 GHz，直流功耗為112.2 mW，平均小訊號增益為12 dB左右。主動式負載分佈式放大器會頻寬為4 ~ 35 GHz，直流功耗為138 mW，平均小訊號增益為11 dB左右。最後會對模擬與量測結果進行討論，針對特性明顯不佳的部分加以修改，並且模擬修改後的電路。
第三章與第四章主要講述開關電容式與開關射極隨偶器兩種不同開關形式之追蹤保持放大器設計分析。在第三章中，追蹤保持電路主要為開關電容式，在設計上使用消除器減少饋通效應，並且使用雜散電晶體減少時脈訊號對保持電位的影響。在前段會先介紹追蹤保持放大器的操作原理與基本組成電路結構，之後則是介紹在設計追蹤保持放大器時會使用到的參數。第四章主要針對於第三章輸出功率較低與設計面積較大的方向進行改進。電路設計上使用修改達靈頓對來增加輸出增益與減少使用電感，達到增加輸出功率與減少佈局面積。兩個章節在電路設計上分為三個部分，分別是輸入緩衝級、輸出緩衝級與開關三個部分。模擬方面會先以理想元件進行評估，再來則使用全波電磁模擬軟體模擬分析佈局對電路設計之影響。之後為量測結果，其中以小訊號S參數、無失真動態範圍與波形圖為主。在量測結果上開關電容式追蹤保持放大器頻寬約為DC-7 GHz，平均增益約為-7 dB，無動態失真範圍在輸入功率為-4 dBm時大於10 dBc，全諧波失真量小於 -10 dBc，消耗直流功率為132 mW。而開關使用射極隨偶器追蹤保持放大器頻寬約為DC-8 GHz，平均增益為-1 dB，無動態失真範圍在輸入功率為-4 dBm時皆大於35 dBc，全諧波失真量小於 -35 dBc，消耗直流功率為84.7 mW。最後兩個設計會針對特性不佳的部分進行修改，並且呈現出改進模擬分析結果。

摘要(英)

This thesis focus on the design and analysis of the high spurious-free dynamic range and low dc power broadband track-and-hold amplifier. The content consists of two distributed amplifiers and two track-and-hold amplifiers. The design goals of the proposed circuits are broadband, high linearity and low dc power consumption. The circuit design, analysis, simulation, and measurement are completely presented in this thesis, and the discussion and conclusion are also addressed for the future works.
Two distributed amplifiers (DAs) are introduced in Chapter 2. To enhance the bandwidth and gain, the DAs are designed sing active and passive loads in the WIN’s 0.15 and 0.25 μm enhancement/depletion-pseudomorphic high-electron mobility transistor (E/D-PHEMT) process, respectively, and some circuit analysis is presented to verify the design methodology. The dc bias and device size selection is addressed with ideal component for the preliminary circuit simulation. The full-wave EM simulator is also adopted to evaluate the layout design. For the experimental results, the small-signal S-parameters, output 1-dB compression point (P1dB) and third-order intercept point (IP3) are completely performed. The measured 3-dB bandwidth of the DA using resistive load is from DC to 63 GHz with an average small-signal gain of 12 dB, and the total DC power consumption is 112 mW. The measured 3-dB bandwidth of the DA using active load is from 4 to 35 GHz with an average small-signal gain of 11 dB, and the DC power consumption is 138 mW.
Two track-and-hold amplifier (THAs) are designed using TSMC 0.18 μm SiGe process in Chapter 3 and 4. The switch capacitor and the switch emitter follower are employed in the track-and-hold stages of the THAs in Chapter 3 and 4, respectively. The introduction and design principle of the THAs are first presented in Chapters. To further reduce the feedthrough during the hold mode, a differential cancellation technique is proposed for the track-and-hold stage designed using switch capacitor. Moreover, the modified Darlington pair is employed to enhance the gain and bandwidth of the THA, and the chip area is also reduced. The full-wave EM simulator is also adopted for the layout designs of the THAs. For the experimental results, the differential small-signal S-parameters, spurious-free dynamic range (SFDR) and time-domain waveform are performed to completely verify the simulations. The measured 3-dB bandwidths of the THAs are both wider than 7 GHz with insertion gains of -7 and -1 dB, respectively. For the THA using switch capacitor with cancellation technique, the measured SFDR and total harmonic distortion (THD) are better than 10 dBc, -10 dBc, respectively, when the input power is -4 dBm. The total DC power consumption is 132 mW. For the THA using switch emitter follower and modified Darlington pair, the SFDR and THD are better than 35 dBc, -35 dBc, respectively, when the input power is -4 dBm. The total DC power consumption is 84.7 mW.

關鍵字(中)

★ 追蹤保持放大器

關鍵字(英)

★ Track-and-Hold Amplifiers

論文目次

第一章緒論 1
1.1 研究動機 1
1.2 相關研究發展 3
1.3 論文貢獻 5
1.4 論文架構 6
第二章分佈式放大器 8
2.1 簡介 8
2.2 分佈式放大器設計概念 8
2.2.1 低頻分析 8
2.2.2 高頻響應分析 12
2.2.3 最佳級數 14
2.3 常數K與M衍生濾波器技術[21] 16
2.3.1 常數K低通(T接面)濾波器 16
2.3.2 M衍生低通(T接面)濾波器技術[21] 18
2.4 負載形式 22
2.4.1 被動式負載(電阻式負載) 22
2.4.2 主動式負載 22
2.5 電阻式負載七級疊接分佈式放大器 25
2.5.1 增益單元設計 25
2.5.2 傳輸線電感設計 29
2.5.3 整體電路模擬 34
2.5.4 量測 42
2.6 主動式六級疊接分佈式放大器 48
2.6.1 增益單元設計 48
2.6.2 傳輸線電感設計 55
2.6.3 修改主動式負載 59
2.6.4 整體電路模擬 62
2.6.5 量測 69
2.6.6 改進 75
2.7 結論 77
第三章使用差動式消除器頻寬為DC ~ 30 GHz追蹤保持放大器 79
3.1 追蹤保持放大器(THA)運作與基本原理 79
3.1.1 追蹤與保持狀態 80
3.2 追蹤鎖定級介紹 80
3.3 設計重點與重要參數介紹[8] 82
3.3.1 擷取時間(Acquisition time, tacq) 82
3.3.2 保持穩定時間(Hold settling time, ths) 83
3.3.3 基底錯誤(Pesestal error) 83
3.3.4 改變率(Droop rate) 83
3.3.5 電賀注入效應(Charge injection) 84
3.3.6 隔離度(Isolation) 84
3.3.7 無失真動態範圍(Spurious-free dynamic range, SFDR) 85
3.4 輸入緩衝級設計 86
3.4.1 增益單元設計 87
3.4.2 電感設計 91
3.4.3 差動架構模擬方法 92
3.4.4 三階諧波失真項(Third harmonic distortion, HD3) 94
3.5 追蹤鎖定級(開關)設計 96
3.5.1 基本PMOS開關 96
3.5.2 饋通訊號(Feedthrough) 98
3.5.3 使用差動式消除器(cancelation) 100
3.5.4 重覆取樣(Resampling) 106
3.5.5 無失真動態範圍(SFDR) 108
3.5.6 使用雜散電晶體 108
3.6 輸出緩衝級 110
3.6.1 疊接傳統放大器架構 110
3.6.2 第三諧波失真項(Third harmonic distortion, HD3) 113
3.7 整體電路模擬 114
3.8 電路實作與量測 121
3.9 改進 129
3.10 研究討論 133
3.11 總結 135
第四章使用修改達靈頓疊接架構的追蹤保持放大器 137
4.1 輸入緩衝級設計 137
4.1.1 達靈頓對(Darlington pair) 137
4.1.2 修改達靈頓對 140
4.1.3 第三諧波失真項(HD3) 143
4.2 輸出緩衝級設計 144
4.2.1 第三諧波失真項(HD3) 145
4.3 追蹤鎖定級設計 146
4.3.1 追蹤狀態 147
4.3.2 保持狀態 148
4.3.3 無失真動態範圍(SFDR) 149
4.4 整體電路模擬 150
4.5 電路實作與量測 157
4.6 改進 164
4.7 總結 166
第五章結論 168

參考文獻

[1] E. L. Ginzton, W. R. Hewlett, J. H. Jasberg, and J. D. Noe, “Distributed amplification,” in Proc. I.R.E., vol. 36, Aug. 1948, pp. 956–969.
[2] 陳汜華，雙閘極元件模型與微波及毫米波分佈式寬頻放大器之研製，第四章，國立中央大學圖書館，民國101年。
[3] P. V. Testa, R. Paulo, C. Carta, and F. Ellinger, “250 GHz SiGe-BiCMOS Cascaded Single-Stage Distributed Amplifier,” in IEEE Compound Semiconductor Integrated Circuit Symp. (CSICS), Dig., pp. 1-4, Oct. 2015.
[4] J. Aguirre, and C. Plett “A 0.1 - 50 GHz SiGe HBT Distributed Amplifier Employing Constant-k m-Derived Sections,” in IEEE MTT-S Int. Micro Symp. Dig., pp. 923-925, June 2003.
[5] P. Chen, J. C. Kao, P.-C. Haung, and H. Wang, “A Novel Distributed Amplifier with High Gain, Low Noise and High Output Power in O.18-μm CMOS Technology,” in IEEE MTT-S Int. Micro Symp. Dig., pp. 1-4. June 2011.
[6] S.-H. Chen, S.-H. Weng, Y.-C. Liu, H.-Y. Chang, J.-H. Tsai, M.-H. Li, and S.-Y. Huang, “A Monolithic DC-70-GHz Broadband Distributed Amplifier Using 90-nm CMOS Process,” presented at the Microw Int. conf., Nuremberg, Germany, pp. 540-543, Oct. 2013.
[7] S. Thijs, D. Linten, C. Pavageau, M. Scholz, and G. Groeseneken, “Center Balanced Distributed ESD Protection for 1-110 GHz Distributed Amplifier in 45 nm CMOS Technology,” in EOS/ESD Symp., Anaheim, CA, pp. 1-6, Sept. 2009.
[8] H.-Y. Chang, Y.-C. Liu, S.-H. Weng, C.-H. Lin, Y.-L. Yeh, and Y.-C. Wang, “Design and analysis of a DC–43.5-GHz fully integrated distributed amplifier using GaAs HEMT-HBT cascode gain stage,” in IEEE Trans. Microw. Theory Techn., vol. 59, no. 2, pp. 443–455, Feb. 2011
[9] H. Shigematsu, N. Yoshida, M. Sato, T. Hirose, and Y. Watanabe, “45-GHz distributed amplifier with a linear 6-Vp-p output for a 40-Gb/s LiNbO modulator driver circuit,” in IEEE Int. GaAs Symp. Dig., vol. 1, pp. 137-140, June 2001.
[10] K.-L Deng, T.-W. Huang, and H. Wang, “Design and analysis of novel high-gain and broad-band GaAs pHEMT MMIC distributed amplifiers with traveling-wave gain stages,” in IEEE Trans. Microw. Theory Techn., vol. 51, pp. 2188–2196, Nov. 2003.
[11] K.-Y. Lin, I.-S. Chen, and H.-K. Chiou, “A 26 - 65 GHz GaAs pHEMT Cascaded Single Stage Distributed Amplifier with High Gain/Area Efficiency,” in Asia-Pacific Microw. Conf., Yokohama, Dec. 2006.
[12] G. Wolf, S. Demichel, R. Leblanc, F. Blache, R. Lefèvre, G. Dambrine1, and H. Happy, “A metamorphic GaAs HEMT Distributed Amplifier with 50 GHz Bandwidth and low Noise for 40 Gbits/s optical receivers,” in IEEE MTT-S Int. Microw. Symp. Dig., pp. 2231–2233, 2005.
[13] A. Martin, T. Reveyrand, M. Campovecchio, R. Aubry, S. Piotrowicz, D. Floriot, and R. Quere, “Design of GaN-based balanced cascode cells for wide-band distributed power amplifier,” presented at the Microw Int. conf., Nuremberg, Germany, pp. 540-543, Oct. 2013.
[14] D. W. Kim, “An Output Matching Technique for a GaN Distributed Power Amplifier MMIC Using Tapered Drain Shunt Capacitors,” in IEEE Microw. Compon. Lett., vol. 25, pp. 603-605, Sept. 2015.
[15] K. W. Kobayashi, D. Denninghoff, and D. Miller, “A Novel 100 MHz-45 GHz GaN HEMT Low Noise Non-Gate-Terminated Distributed Amplifier based on a 6-inch 0.15 μm GaN-SiC mm-Wave Process Technology,” IEEE Compound Semiconductor Integrated Circuit Symp. (CSICS), Dig., pp. 1-4, Oct. 2015.
[16] S. Masuda, et al., “An over 1 10-GHz InP HEMT flipchip distributed baseband amplifier with inverted microstrip line structure for optical transmission systems,”, J. Solid-State Circuits, vol. 38, no. 9, pp. 1479- 1484, Sept. 2003.
[17] C. Meliani, G. Rondeou, G. Post, J Decoberr. Iy. Mouronnar. E. Durisseuil. and R. Lefevre. "A high gain-bandwidth product InP HEMT dirtributed amplifier with 92 GHz cut-off frequency for 40 Gbit/s applications and beyond,". Gallium Arsenide Inregrated Circuir lGaAs IC) Symposium, 2002. Monterey, CA. 241h Annsol Technical Digesl , pp. 103- 106
[18] M. A. Reza, C. K. Nishimoto, M. Riaziat, M. Glenn, S. Silverman, S. L. Weng, Y. C. Pao, and G. A. Zdasiuk, “5-100 GHz InP Coplanar Waveguide MMIC Distributed Amplifier,” in IEEE Trans. Microw. Theory Techn., vol. 38, pp. 1986-1993, Dec. 1990.
[19] B. Y. Banyamin, and M. Berwick, “Analysis of the performance of four-cascaded single-stage distributed amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 48, no. 12, pp.2657–2663, Dec. 2000.
[20] Y. Suzuki, Z. Yamazaki, and H. Hida, “An 80-Gb/s 2.7-Vpp driver IC based on functional distributed circuits for optical transmission systems,” in RFIC Symp. Dig. Papers, 2005, pp. 325–328.
[21] D. M. Pozar, “Microwave Engineering,” Chapter 8, 3rd Ed. New York: Wiley, 2005.
[22] B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995.
[23] R. Bayruns, N. Scheinberg, and R. Goyal, “An 8-11s monolithic GaAs sample and hold amplifier,” in ISSCC Dig. Tech. Papers, 1987, pp. 42-43.
[24] Y. Borokhovych, H. Gustat, B. Tillack, B. Heinemann, Y. Lu, W. Kuo, X. Li, R. Krithivasan, and J.D Cressler, "A low-power, 10GS/s trackand-hold amplifier in SiGe BiCMOS technology," to appear in 31st Euro. Solid-State Circuits Conf., Sept. 2005.
[25] P. Zammit, I. Grech, J. Micallef, and E. Gatt, “A 10 Gsamples/s SiGe Track-and-Hold Amplifier with 8-bit Resolution,” in Proc. IEEE-ICECS, Morocco, 2007, pp. 190–193.
[26] S. Shahramian, S. P. Voinigescu, and A. C. Carusone, “A 35-GS/s, 4-Bit flash ADC with active data and clock distribution trees,” IEEE J. Solid-State Circuits, vol.44, pp.1709-1720, June 2009.
[27] X. Li, W.-M. L. Kuo, and J. D. Creeler, “A 40 GS/s SiGe track-and-hold amplifier,” IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Oct. 2008, pp. 1-4.
[28] X. Li, W. L. Kuo, Y. Lu, R. Krithivasan, J. D. Cressler, and A. J. Joseph, “A 5-bit, 18 GS/sec SiGe HBT track-and-hold amplifier,"in IEEE Compound Semiconductor Integrated Circuit Symposium, Nov. 2005, pp. 105-108.
[29] D. Cascella, G. Avitabile, F. Cannone, and G. Coviello, “A 2-GS/s 0.35µm SiGe track-and-hold amplifier with 7-GHz analog bandwidth using a novel input buffer,” in 18th IEEE Int. Conf. on Electron Circuits Syst. (ICECS), pp. 113-116, Dec. 2011.
[30] F. Vessal, and C. Salama, "A bipolar 2-GSample/s track-and-hold amplifier (THA) in 0.35 µm SiGe technology," in IEEE Proc. ISCAS, vol. 5, pp. 573-576, May 2002.
[31] S. Shahramian, A. C. Carusone, and S. P. Voinigescu, “A 40-GSamples/Sec Track & Hold Amplifier in 0.18μm SiGe BiCMOS Technology” in IEEE Compound Semiconductor Integrated Circuit Symp. (CSICS), Dig., Oct. 2005.
[32] S. Shahramian, and A. C. Carusone, “Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-μm SiGe BiCMOS Technology,” in IEEE J. Solid-State Curicuit (CICC), pp. 493-496, Oct. 2006.
[33] D. Lal, M. Abbasi, and D. S. Ricketts, “A Compact, High Linearity 40GS/s Track-and-Hold Amplifier in 90nm SiGe Technology,” in IEEE Custom Integrated Circuit Conf. (CICC)., pp. 1-4, Sept. 2015.
[34] Y. Zhang, Q. Meng, Q. Huang, and K. Tang, “A Track-and-Hold Amplifier for 1GSps 8bit ADC in 0.18-μm CMOS Process,” in Int. Conf. Advanced Technol. Commun. (ATC)., pp. 5-8, Oct. 2012.
[35] D. Vecchi, C. Azzolini, A. Boni, F. Chaahoub, and L. Crespi, “100-MS/s 14-b Track-and-Hold Amplifier in 0.18-μm CMOS,” to appear in 31st Euro. Solid-State Circuits Conf., pp. 259-262, Sept. 2005.
[36] H. Orser, and A. Gopinath, “A 20 GS/s 1.2 V 0.13 μm CMOS switched cascode track-and- hold amplifier,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol.57, pp. 512-516, July 2010.
[37] Y.-C. Liu, H.-Y. Chang, and K. Chen, “A 12 GB/s 3-GHz input bandwidth track-and-hold amplifier in 65 nm CMOS with 48-dB spur-free dynamic range,” in IEEE MTT-S Int. Microw. Symp. Dig., Florida, USA, June 2014.
[38] S. Ma, J. Wang, H. Y, and J. Ren, “A 32.5-GS/s Two-Channel Time-Interleaved CMOS Sampler with Switched-Source Follower based Track-and-Hold Amplifier,” in IEEE MTT-S Int.l Microw Symp. Dig., Florida, USA, June 2014.
[39] Y.-C. Liu, H.-Y. Chang, S.-Y. Hung, and K. Chen, “Design and Analysis of CMOS High-Speed High Dynamic-Range Track-and-Hold Amplifiers,” IEEE Trans.Microw. Theory Techn., vol. 63, pp. 2841-2853, Spet. 2015.
[40] H. Aggrawal, and A. Babakhani, “A 40GS/s Track-and-Hold Amplifier with 62dB SFDR3 in 45nm CMOS SOI,” in IEEE MTT-S Int.l Microw Symp. Dig., Florida, USA, June 2014.
[41] J. Lee, A. Leven, J. S. Weiner, Y. Baeyen, Y. Yang, and W.-J. Sung, et al., “A 6-b 12-GSamples/s track-and-hold amplifier in InP DHBT technology,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 1533-1539, June 2003.
[42] J. Deza, A. Ouslimani, A. Konczykowska, A. Kasbari, and J. Godin, “A 4 GSa/s, 16-GHz input bandwidth master-slave track-and-hold amplifier in InP DHBT Technology,” 20th Telecommun. Forum, pp. 502–505, Nov. 2012.
[43] Y. Bouvier, A. Ouslimani, A. Konczykowska, and J. Godin, “A 40 GSamples/s InP-DHBT Track-and-Hold Amplifier with High Dynamic Range and Large Bandwidth,” Int. Symp. Commun. Syst. Netw. Digit. Signal. Process., pp. 1-4, July 2012.
[44] K. N. Madsen, T. D. Gathman, S. Daneshgar, T. C. Oh, J. C. Li, and J. F. Buckwalter, “A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process,” in IEEE J. Solid-State Circuits, pp. 2692-2702, Oct. 2015.
[45] Y. Bouvier, A. Ouslimani, A. Konczykowska, and J. Godin, “A 1-GSample/s, 15-GHz inputbandwidth master–slave track-and-hold amplifier in InP DHBT technology,” IEEE Trans.Microw. Theory Techn., vol. 57, pp. 3181-3187, Dec. 2009.
[46] S.-H. Weng, “Monolithic Microwave and Millimeter-wave Broadband Circuits using Darlington Cell,” Ph.D.dissertation, Dept. Electron. Eng. National Central Univ., Chungli, Tiawan, 2013.

指導教授

張鴻埜(Hong-yeh Chang)

審核日期

2016-1-26

推文