參考文獻 |
[1] P. R. Troyk and G. A. DeMichele, “Inductively-coupled power and data link for neural prostheses using a class-E oscillator and FSK modulation,” in Proc. IEEE 25th EMBS Conf., vol. 4, pp. 3376–3379, Sept. 2003.
[2] J.-H Song, C. Cui, and S.-K. Kim, “A low-phase-noise 77-GHz FMCW radar transmitter with a 12.8-GHz PLL and a ×6 frequency multiplier,” IEEE Microw. Wireless Compon. Lett., vol. 26, no. 7, pp. 540–542, Jul. 2016.
[3] K.-Y Lin, J.-Y. Huang, J.-L. Kuo, C.-S. Lin, and H. Wang, “A 14-23 GHz CMOS MMIC distributed doubler with a 22-dB fundamental rejection,” in IEEE MTT-S Int. Microw. Symp. Dig., pp. 1477-1480, Jun. 2008.
[4] F. Ellinger and H.Jackel, “Ultracompact SOI CMOS frequency doubler for low power applications at 26.5-28.5 GHz,” IEEE Microw. Wireless Compon. Lett., vol. 14, no. 2, pp. 53–55, Feb. 2004.
[5] H. Zirath, T. Masuda, R. Kozhuharov, and M. Ferndahl, “Development of 60 GHz front-end circuits for a high-data-rate communication system,” IEEE J. Solid-State Circuits, vol. 39, no. 10, pp. 1640–1649, Oct. 2004.
[6] Y. Liu, T. Yang, Z. Yang, and J. Chen, “A 3-50 GHz ultra-wideband pHEMT MMIC balanced frequency doubler,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 9, pp. 629–631, Sept. 2008.
[7] C.-C Weng, Z.-M Tsai, and H. Wang, “A K-band miniature, broadband, high output power HBT MMIC balanced doubler with integrated balun,” in Proc. Eur. Micro. Integr. Circuits Conf., vol. 3, pp. 1–3, Oct. 2005.
[8] D.-W. Kang, D.-H Baek, S.-H. Jeon, J.-W Park, and S. Hong, “A 14-23 GHz CMOS MMIC distributed doubler with a 22-dB fundamental rejection,” in IEEE MTT-S Int. Microw. Symp. Dig., pp. 107-110, Jun. 2003.
[9] B. Razavi, RF Microelectronics, Prentice Hall, 1998.
[10] A. S. Sedra and K. C. Smith, Microelectronic Circuits, Oxford, New York, pp. 1112-1113, 1998.
[11] F. Maloberti and M. Signorelli, “Quadrature waveform generator with enhanced performances,” Symposium on VLSI Circuits Digest of Technical Papars, pp. 56-57, 1998.
[12] M. Tormanen and H. Sjoland, “A 26-GHz LC-QVCO in 0.13-m CMOS,” in Proc. Asia–Pacific Microw. Conf., pp. 1769–1772, Dec. 2007.
[13] S. Hackl, J. Bock, G. Ritzberger, M. Wurzer, and A. L. Scholtz, “A 28-GHz monolithic integrated quadrature oscillator in SiGe bipolar technology,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 135–137, Jan. 2003.
[14] M. Tormanen and H. Sjoland, “A 24-GHz LC-QVCO in 130-nm CMOS using 4-bit switched tuning,” in Proc. IEEE Int. Microelectron. Conf., Sharjah, U.A.E., pp. 462–465, Dec. 2008.
[15] M. Hossain and A. C. Carusone, “20 GHz low power QVCO and de-skew techniques in 0.13 m digital CMOS,” in Proc. IEEE Custom Integr. Circuits Conf., pp. 447–450, Sept. 2008.
[16] M. Sanduleanu and E. Stikvoort, “Highly linear, varactor-less, 24-GHz IQ oscillator,” in IEEE RFIC Symp. Dig., pp. 577–580, Jun. 2005.
[17] M. Tormanen and H. Sjoland, “A 24-GHz quadrature receiver front-end in 90-nm CMOS,” in Proc. IEEE Asia–Pacific Microw. Conf., pp. 1152–1155, Dec. 2009.
[18] S. B. Shin, H. C. Choi, and S.-G. Lee, “Source-injection parallel coupled LC-QVCO,” in Electron. Lett., vol. 39, no. 14, pp. 1059–1060, Jul. 2003
[19] S. J. Yun, D. Y. Yoon, and S. G. Lee, “A complementary CMOS LC quadrature oscillator,” IEICE Trans. Electron., vol. E91-C, no. 11, pp. 1806–1810, Nov. 2008.
[20] H. Kim, C. Cha, S. Oh, M. Yang, and S. Lee, “A very low-power quadrature VCO with back-gate coupling,” IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 952–955, Jun. 2004.
[21] R. C. H. v. d. Beek, C. S. Vaucher, D. M. W. Leenaerts, E. A. M. Klumperink, and B. Nauta, “A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-µm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1862–1872, Nov. 2004.
[22] D. Murphy, Q. J. Gu, Y.-C. Wu, H.-Y. Jian, Z. Xu, A. Tang. F. Wang, and M.-C. F. Chang, “A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c transceiver,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1606–1617, Jul. 2011.
[23] Z. Xu, Q. J. Gu, Y.-C. Wu, H.-Y. Jian and M.-C F. Chang, “A 70-78 integrated CMOS frequency synthesizer for W-band satellite communications,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 12, pp. 3206–3218, Dec. 2011.
[24] G.-Y. Chen, S.-H. Weng, H.-Y. Chang, and Y.-M. Hsin, “A K-band high performance frequency quadrupler using CG-CS balanced configuration in E/D-mode PHEMT Process,” in Proc. Eur. Micro. Integr. Circuits Conf., pp. 249–252, Oct. 2014.
[25] G.-Y. Chen, H.-Y. Chang, S.-H. Weng, and Y.-M. Hsin, “A Ka-band broadband active frequency doubler using CB-CE balanced configuration in 0.18-µm SiGe BiCMOS process,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2012.
[26] I. R. Chamas and S. Raman, “Analysis, design, and X-band implementation of a self-biased active feedback Gm-boosted common-gate CMOS LNA,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 3, pp. 542–551, Mar. 2009.
[27] W. Zhou, X. Li, S. Shekhar, S. H. K. Embabi, J. P. de Gyvez, D. J. Allstot, and E. Sanchez-Sinencio, “A capacitor cross-coupled common-gate low-noise amplifier,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 12, pp. 875–879, Dec. 2005.
[28] X. Li, S. Shekhar, and D. J. Allstot, “Gm-boosted common-gate LNA and differential Colpitts VCO/QVCO in 0.18-µm CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2609–2619, Dec. 2005.
[29] I. R. Chamas and S. Raman, “Analysis, design, and X-band implementation of a self-biased active feedback Gm-boosted common-gate CMOS LNA,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 3, pp. 542-551, Mar. 2009.
[30] F. Belmas, F. Hameau, and J. Fournier, “A low power inductorless LNA with double Gm enhancement in 130 nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 5, pp. 1094-1103, Mar. 2012.
[31] G. Gonzalez, Microwave Transistor Amplifiers Analysis and Design, Prentice Hall, 1997.
[32] J. M. Rollet, “Stability and power gain invariants of linear two-ports,” IRE Trans. on Circuit Theory, vol. CT-9, no. 5, pp. 29-32, 1962.
[33] M. L. Edwards and J. H. Sinsky, “A new criterion for linear 2-port stability using a single geometrically derived parameter,” IEEE Trans. Microw. Theory Tech., vol. 40, no. 12, pp. 2303-2311, Dec. 1992.
[34] R. J. Weber, “Even mode and odd mode stability,” 40th Midwest Symposium on Circuits and Systems, pp. 607-610, Aug. 1997.
[35] E. L. Tan, “Rollett-based single-parameter criteria for un-conditional stability of linear two-ports,” IEE Microw. Antennas Propag., vol. 5, no. 1, pp. 30-37, Jan. 2011.
[36] J. J. Hung, T. M. Hancock, and G. M. Rebeiz, “High power high efficiency SiGe Ku and Ka-band balanced frequency doublers,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 2, pp. 754–761, Feb. 2005.
[37] Y. C. Li, F.-H. Huang and Q. Xue, “20–40 GHz dual-gate frequency doubler using 0.5 μm GaAs pHEMT technology,” in Electronics Letters, vol. 50, no. 10, pp. 758–759, May 2014.
[38] S. Hackl and J. Bock, “42 GHz active frequency doubler in SiGe bipolar technology,” in Proc. 3rd Int. Microwave and Millimeter Wave Technology Conf. Papers, pp. 54–57, Aug. 2002.
[39] 陳冠宇,“微波毫米寬頻高效率倍器之研製”,國立中央大學電機工程研究所博士論文,民國 103 年6 月。
[40] S. Wang and C.-T. Chang, “K-band CMOS frequency doubler with high fundamental rejection,” in Electronics Letters, pp. 1211–1212, Aug. 2014.
[41] M. Ferndahl, B. M. Motlagh, and H. Zirath, “40 and 60 GHz frequency doublers in 90-nm CMOS,” in IEEE MTT-S Int. Microw. Symp. Dig., pp. 179–182, Jun. 2004.
[42] M. Mizan, D. Sturzbecher, T. Higgins, and A. Paolella, “An X-band, high power dielectric resonator oscillator for future military systems,” IEEE Trans. Ultrason. Ferroelectr. Freq. Control., vol. 40, no. 5, pp. 483–487, Sept. 1993.
[43] D. Shen, L. Jin, and L.L. Zhou, “A L-band transceiver front-end for ADS-B system,” Int. Workshop on Microwave and Milimeter Wave Circuits and System Technology (MMWCST), 19-20 Apr. 2012, pp. 1–3.
[44] Y.-S. Lin, C.-C. Wang, P.-W. Yu, J.-H. Lee, and S.-S. Lu, “Low-phase-noise 0.63-V, 1.7-mW, 11.55-GHz quadrature voltage controlled oscillator with intrinsic-tuned technique in 0.18-μm complimentary metal oxide semi-conductor,” IET Microw. Antennas Propag., vol. 6, no. 13, pp. 1437–1442, May. 2009.
[45] J. Lin, Y. K. Chen, D. A. Humphrey, R. A. Hamm, R. J. Malik, Al Tate, R. F. Kopf, and R. W. Ryan, “Ka-band monolithic InGaAs/InP HBT VCO’s in CPW structure,” IEEE Micro. Guided Wave Lett., vol. 5, no. 11, pp. 379–381, Nov. 1995.
[46] E. Juntunen, D. Dawn and J. Laskar, “High-power, high-efficiency CMOS millimetre-wave oscillators,” IET Trans. Microw., Antennas, Propag., pp. 1158–1163, Aug. 2012.
[47] E. Juntunen, D. Dawn and J. Laskar, “A high-efficiency, highpower millimeter-wave oscillator using a feedback class-E power amplifier in 45-nm CMOS,” IEEE Microw. Wireless Compon. Lett., pp. 430–432, 2011.
[48] C.-Y. Kim, J. Yang, D.-W. Kim, and S. Hong, “A K-band quadrature VCO based on asymmetric coupled transmission lines,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2008, pp. 363–366.
[49] K. L. Kotzebue and W. J. Parrish, “The use of large signal S-parameters in microwave oscillator design,” in Proc. 1975 Int. Microw. Symp. on Circuit and Systems.
[50] K. M. Johnson, “Large Signal GaAs MESFET oscillator design,” IEEE Trans. Microw. Theory Tech., vol. 27, no. 3, pp. 217–227, Mar. 1979.
[51] S. Jeon, A. Suarez and D. B. Rutledge, “Nonlinear design technique for high-power switching-mode oscillators,” IEEE Trans. Microw. Theory Tech., vol. 54, pp. 3630-3640, Oct. 2006.
[52] D. B. Lesson, “A simple model of feedback oscillator noise spectrum,” Proc. IEEE., vol. 54, pp. 329-330, Feb. 1966.
[53] 李文賓,“高功率高效率振盪器研製”,國立中央大學電機工程研究所碩士論文,民國 100 年7 月。
[54] H.-Y. Chang, Y.-S. Wu, and Y.-C. Wang, “A 38% tuning bandwidth low phase noise differential voltage controlled oscillator using a 0.5 μm E/D-PHEMT process,” IEEE Microw. Wireless Common. Lett., vol. 19, no. 7, pp. 467–496, Jul. 2009.
[55] “Optimization of quadrature modulator performance,” Technical Notes and Articles, RF Micro Devices Inc.
[56] 邱垣達,“低功耗低相位雜訊差動及四相位單晶微波積體電路壓控振盪器之研究”,國立中央大學電機工程研究所碩士論文,民國100年6月。
[57] 廖彥涵,“微波毫米波寬頻振盪器與鎖相迴路之研製”,國立中央大學電機工程研究所碩士論文,民國102年3月。
[58] B. Liang, “Analyze and design 10-GHz 0.8-VDD -117dBc/Hz quadrature LC-VCO in 120 nm CMOS technology,” IEEE Green Circuits and Systems, pp. 420– 423, 2010.
[59] S. Ko, “20 GHz Integrated CMOS frequency sources with a quadrature VCO using transformers,” in 2004 IEEE RFIC Symp. Dig., Jun. 2004, pp. 269–272.
[60] C. H. Lin, “A low phase noise low dc power quadrature voltage-controlled oscillator using a 0.18-µm CMOS process,” in Eur. Microw. Integrated Circuits Conf., 2009 (EuMIC), Sept. 28-29, 2009, pp. 112-115.
[61] I. S. Shen and C. F. Jou, “A X-Band capacitor-coupled QVCO using sinusoidal current bias technique,” Int. Solid-State Circuits Conf. in Proc. (ISSCC), 2012, pp. 318–328.
[62] 林紀賢,“注入鎖定非線性單晶微波積體之研究”,國立中央大學電機工程研究所博士論文,民國101年11月。
[63] J. Lee and B. Razavi, “A 40-GHz frequency divider in 0.18-µm CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 594–601, Apr. 2004.
[64] H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813–821, Jun. 1999.
[65] Y. Mo, E. Skafidas, R. Evans, and I. Mareels, “Superharmonic injection-locked frequency dividers,” IEEE ICCSC 2008, pp. 812–815.
[66] Z. Deng and A. M. Niknejad, “The speed-power trade-off in the design of CMOS true-single-phase-clock dividers,” IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2457–2465, Nov. 2010.
[67] M. Soyuer and R. G. Meyer, “Frequency limitations of a conventional phase-frequency detector,” IEEE J. Solid-State Circuits, vol. 25, no. 4, pp. 1019–1022, Aug. 1990.
[68] 劉深淵及楊清淵,“鎖相迴路”,民國97年2月。
[69] B.-Y. Lin, and S.-I. Liu, “A capacitor cross-coupled common-gate low-noise amplifier,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 10, pp. 617–621, Oct. 2011.
[70] K. Tsutsumi et al., “Low phase noise Ku-band PLL-IC with -104.5 dBc/Hz at 10-kHz offset using SiGe HBT ECL PFD,” in Proc. Asia–Pacific Microw. Conf., pp. 373–376, Dec. 2009.
[71] S.-Y. Yang, W.-Z. Chen, and T.-Y. Lu, “A 7.1 mw, 10 GHz all digital frequency systhesizer with dynamically reconfigured digital loop filter in 90 nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 578–586, Mar. 2010.
[72] J.-Y. Lee, “A 9.1-to-11.5-GHz Four-Band PLL for X-Band Satellite & Optical Communication Applications,” in IEEE RFIC Symp. Dig., pp. 338–339, Jun. 2007.
[73] I.-W. Tseng and J.-M. Wu, “An 18.7mW 10-GHz phase-locked loop circuit in 0.13-µm CMOS,” VLSI-DAT ’09, pp. 227-230.
[74] J.F Huang, “Chip Design of 10 GHz Low Phase Noise and Small Chip Area PLL,” IEEE Communications and Networking in China (CHINACOM), pp. 276–280, Aug. 2013.
[75] T.-H. Lin, “An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL,” IEEE J. Solid-State Circuits, vol. 42, no. 2, Feb. 2007.
[76] R. C. H. van de Beek, C. S. Vaucher, D. M. W. Leenaerts, Eric A. M. Klumperink, and B. Nauta, “A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-µm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 11, Nov. 2004.
[77] N. Pavlovic, J. Gosselin, K. Mistry, and D. Leenaerts, “A 10 GHz frequency synthesizer for 802.11a in 0.18-µm CMOS,” in Proc. IEEE Eur. Solid-State Circuits Conf., pp. 367-370, Sept. 2004.
[78] A. Rofougaran, J. Rael, M. Rofougaran and A. Abidi, “A 900 MHz LC-oscillator with quadrature outputs,” in 1996 Int. Solid-State Circuits Conf. Dig., pp. 392-393.
[79] 張盛富及張嘉展,“無限通訊射頻晶片模組設計-射頻晶片篇”,民國97年6月。
[80] X. Gao, E. A. M. Klumperink, P. F. J. Geraedts, and B. Nauta, “Jitter analysis and a benchmarking figure-of merit for phase-locked loops,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 2, pp. 117–121, Feb. 2009.
[81] 陳仕鴻,“數位無線通訊系統應用之低電壓高功率砷化鎵場效電晶體研究”,國立交通大學材料科學與工程系博士論文,民國91年11月。 |