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姓名 張哲瑋(Che-Wei Chang)  查詢紙本館藏   畢業系所 電機工程學系
論文名稱 具矽基板貫孔之鐵電可變電容的製作與量測
(Fabrication and Measurement of Ferroelectric Varactors with Through Substrate Vias on Silicon)
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摘要(中) 鐵電可變電容具有高電容密度、高可調度、低操作電壓及較低的製程複雜度等優點。由於鐵電薄膜在鍍製或退火時須處在高溫的環境下,因此平行板結構的鐵電可變電容的下電極不能太厚,否則將在高溫下將會變得粗糙,對電容品質造成影響。然而,由於厚度薄的下電極會造成較大的射頻損耗,鐵電可變電容的品質因子往往因此受限。為改善鐵電可變電容的品質因子,我們提出,在高溫製程完成後,從基板背面製作貫孔來揭露下電極,並續以電鍍的方式來增厚下電極。
在本研究中,我們發展矽基板貫孔製程來實現具厚電極的鐵電可變電容。在第二章中,我們詳細說明所提出的具厚電極的鐵電可變電容電極的結構及製作流程;在第三章則呈現量測結果。量測結果顯示,鐵電可變電容可調度在偏壓10 V時約為1.3:1,而品質因子於2.4 GHz下則約為10。量測到的品質因子並沒有改善;究其原因,我們由GSG(ground–signal–ground)開路測試結構的量測結果發現所使用的高電阻率矽基板其射頻損耗並不如預期中的小。若將GSG pad的效應以去嵌入(de-embedding)的方式扣除,鐵電可變電容於2.4 GHz的品質因子可以從原本的10上升至40左右。
我們成功地發展出具矽基板貫孔之鐵電可變電容之製作流程。雖然量測結果尚未能驗證品質因子的改善,但我們已發現原因是由於高電阻率矽基板其射頻損耗過大所致。未來我們將在製程中加入可穩化高電阻率矽基板的工序,使其呈現應有的低損耗特性。
摘要(英) Compared with other varactor technologies, the ferroelectric varactor possesses the advantages of high capacitance density, high tunability, low bias voltage, and low fabrication complexity. Because ferroelectric thin film often undergoes high-temperature process during either the deposition or the post-annealing, the bottom electrode of a parallel-plate-based ferroelectric thin-film varactor must be thin enough to avoid being roughened under such high temperature, which would degrade the quality of the ferroelectric thin film. However, the thin bottom electrode, which causes higher radio-frequency (rf) loss, often limits the quality factor of the ferroelectric varactors. To solve this problem, we propose to expose the bottom electrode by making a via-hole from the backside of the substrate after the high-temperature process is done and then thicken the bottom electrode by electroplating.
In this work, we develop a through-substrate-via fabrication process on silicon to implement ferroelectric varactors with thick electrodes. In Chapter 2, the structure and the fabrication process of the proposed ferroelectric varactor with thick electrodes are described, whereas the measurement results are presented in Chapter 3. Measurement results shown that, the fabricated ferroelectric varactor exhibits a tunability of 1.3:1 under 10-V bias and its quality factor at 2.4 GHz is about 10. The measured quality factor unfortunately does not see improvement. Nevertheless, by the measurement result of the GSG (ground–signal–ground) open-circuit test structure, we find that it is because the rf loss of the high-resistivity silicon substrate in use is not as small as expected. If the effect of GSG pad is de-embedded, the quality factor of the ferroelectric varactor is increased from the original 10 to about 40.
To conclude, we have successfully developed the fabrication process of ferroelectric varactors with through substrate vias on silicon. Though the measurement results have not yet demonstrated the expected improvement of the quality factor, we have found that it is due to the high rf loss caused by the high-resistivity silicon substrates we use. In the future, we plan to incorporate into our fabrication process the procedures that stabilize the high-resistivity silicon, making the substrate to exhibit the expected low-loss property.
關鍵字(中) ★ 鐵電可變電容
★ 基板貫孔技術
關鍵字(英) ★ ferroelectric varactor
★ through substrate vias
論文目次 目錄
國 立 中 央 大 學 I
摘要 I
Abstract II
誌謝 IV
目錄 V
圖目錄 VII
表目錄 X
第一章 緒論 1
1–1 研究動機 1
1–2 可變電容技術介紹 3
1–3 鐵電材料特性 5
1–4 章節介紹 7
第二章 具矽基板貫孔之鐵電可變電容電容製作 8
2–1 簡介 8
2–2 具有矽基板貫孔之鐵電平行板電容光罩設計 10
2–3 具矽基板貫孔之鐵電可變電容製作流程 15
2–3–1 下電極製作流程 15
2–3–2 鐵電薄膜之沉積 18
2–3–3 上電極製作流程 19
2–3–4 鐵電薄膜介電層製作流程 21
2–3–5 氮化矽保護層之沉積與製作流程 23
2–3–6 接腳層(pad)製作流程 26
2–3–7 矽基板貫孔(Through Substrate Vias, TSV)製作流程 33
2–3–8 BCB保護層之開孔 39
第三章 矽基板貫孔之應用量測與分析 42
3–1 矽基板貫孔之應用量測結果 42
3–1–1 矽基板貫孔結構電感與等效阻抗值量測結果 43
3–1–2 具矽基板貫孔之鐵電可變電容量測容結果 48
3–2 具矽基板貫孔之鐵電可變電容分析與討論 56
第四章 結論 64
4–1 結果與討論 64
4–2 未來研究方向 65
參考文獻 66
附錄 67
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[7] M. Sazegar, Y. Zheng, H. Maune, C. Damm, X. Zhou, J. Binder, and R. Jakoby, “Low-cost phase-array antenna using compact tunable phase shifters based on ferroelectric ceramics,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 5, pp. 1265–1273, May 2011.
[8] Y. Lu, “RF MEMS devices and their applications in reconfigurable RF/microwave circuits,” Ph.D. dissertation, The University of Michigan, Ann Arbor, MI, USA, 2005.
[9] S. Gevorgain, Ferroelectrics in Microwave Devices, Circuits and Systems, 1st ed. London: Springer-Verlag, 2009.
[10] M. Norling, D. Kuylenstierna, A. Vorobiev, and S. Gevorgian, “Layout optimization of small-size ferroelectric parallel-plate varactors,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 6, June 2010.
[11] H. S. Gamble, B. M. Armstrong, S. J. N. Mitchell, Y. Wu, V. F. Fusco, and J. A. C. Stewart, “Low-loss CPW line on surface stabilized high-resistivity silicon,” IEEE Microwave And Guided Wave Letters, vol. 9, No. 10, October 1999.
[12] B. Rong, J. N. Burghartz, L. K. Nanver,, B. Rejaei, and M. van der Zwan, “Surface-passivated high-resistivity silicon substrates for RFICs,” IEEE Electron Device Letters, vol. 25, No. 4, April 2004.
指導教授 傅家相(Jia-Shiang Fu) 審核日期 2016-1-5
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