應用於C/X 頻段之低功耗寬頻前端電路接收機暨寬頻低雜訊放大器之研製

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：86

、訪客IP：3.149.239.209

姓名

蕭仲華(Chung-Hua Hsiao) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於C/X 頻段之低功耗寬頻前端電路接收機暨寬頻低雜訊放大器之研製
(Implementations on Low Power Wideband Receiver Front-End and Wideband Low Noise Amplifier for C/X Band Applications)

相關論文

★ 應用於筆記型電腦數位電視單極天線之研製	★ 應用於數位機上盒與纜線數據機之電纜多媒體傳輸標準多工濾波器
★ 印刷共面波導饋入式多頻帶與超寬頻天線設計	★ 微波存取全球互通頻段前向匯入式功率放大器與高效率Class F類功率放大器暨壓控振盪器電路之研製
★ 應用於矽基功率放大器與混頻器之傳輸線型變壓器研究	★ 應用於V-頻段射頻收發機前端電路之低功耗源極注入式混頻器之研製
★ 應用積體電路上方後製程與整合被動元件於互補式金氧半導體製程之系統封裝研究	★ 應用fT-倍頻電路架構於毫米波壓控振盪器與注入鎖定除頻器之研製
★ 應用傳輸線型變壓器於X/K–Ka/V頻段全積體整合之寬頻互補式金氧半導體功率放大器研製	★ 應用於K / V 頻段低功耗混頻器之研製
★ 應用於K/V頻段之低功耗CMOS低雜訊放大器之研究	★ 應用於5-GHz CMOS射頻前端電路之低電壓自偏壓式混頻器與高線性化功率放大器之研製
★ 應用於 K 頻段射頻接收機之寬頻低功耗 CMOS 低雜訊放大器之研製	★ 應用磁耦合變壓器於K頻段之低功耗互補式金氧半導體壓控振盪器研製
★ 應用於K頻段之單向化全積體整合功率放大器與應用於V頻段之寬頻功率放大器研製	★ 應用於C/X頻段全積體整合之互補式金氧半導體寬頻低功耗降頻器與寬頻功率混頻器之研製

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 ( 永不開放)

摘要(中)

此論文採用tsmcTM CMOS 0.18 μm 製程設計C/X頻段之寬頻低雜訊放大器以及前端接收機，研究的方向以寬頻、低功耗為設計目標。
第一顆電路使用三級串聯之寬頻低雜訊放大器，為了達到寬頻的輸入匹配，第一級使用了共閘級架構，第二級和第三級以提升增益為目標使用了共源極架構，且三級都使用了汲極至源極變壓器回授技術來進行設計，達到降低雜訊以及增益平坦的效果。本電路增益為13.66 dB，3-dB頻寬從7.19 GHz-13 GHz，雜訊最小值為4 dB，P1dB量測結果為-12 dBm，IIP3則為-2.6 dBm，量測功耗為10.7 mW，晶片面積為0.96 × 0.93 mm2。
第二顆電路使用反向放大架構結合電阻回授之寬頻低雜訊放大器，為了減小輸入匹配寬頻的面積使用，第一級採用反向放大架構且將閘極與源極電感整合為變壓器，第二級使用共源極回授架構來節省面積，結合了汲極至源極變壓器回授來達到增益平坦。本電路增益為11.56 dB，3-dB頻寬從4.9 GHz-11.7 GHz，雜訊最小值為3.5 dB，P1dB量測結果為-12 dBm，IIP3則為-1.9 dBm，量測功耗為8.7 mW，晶片面積為0.73 × 0.68 mm2。
第三顆電路為低功耗寬頻直接降頻接收機，接收機電路架構包含寬頻低雜訊放大器、平衡與不平衡轉換變壓器、寬頻電流模態被動混波器、中頻放大器。為了改善雜訊以及功耗，低雜訊放大器另外設計並非採用第一顆電路的架構；平衡與不平衡轉換變壓器採用電感式耦合共振器的技術來達到寬頻且小面積，且不消耗任何功耗。量測結果的電壓轉換增益為30.03 dB，3-dB頻寬從4.5 GHz-11.7 GHz，雙邊帶雜訊指數最小值為9.2 dB，P1dB量測結果為-21 dBm，IIP3為-14.3 dBm，IIP2則為35.7 dBm，在系統電壓1.8 V下功耗為10.96 mW，晶片面積為2.38 × 0.94 mm2。

摘要(英)

This thesis develops two circuit designs in tsmcTM 0.18 μm CMOS technology. The primary target of the thesis is to design wideband and low power consumption.
The first circuit is a wideband low noise amplifier which employs three stage cascade topology. In order to achieve wideband matching, the first stage used common gate topology. Then, the second stage and third stage used common source topology to enhance gain. The circuit adopted the drain to source transformer feedback techniques, and this technique successfully lowered the noise figure and flatted the gain. The proposed LNA achieves a gain of 13.66 dB over a 3-dB bandwidth from 7.19 to 13 GHz with a minimum noise figure (NF) of 4 dB. The measured P1dB is -12 dBm and the IIP3 is -2.6 dBm. The power consumption of the LNA is 10.7 mW. The chip size is 0.96 × 0.93 mm2.
The second circuit is a wideband low noise amplifier which employs the inverter type with resistor feedback topology. In order to reduce the area of the input matching network, the first stage used inverter type topology and integrated the gate and source inductor into transformer. Then, the second stage used resistive feedback common source topology to reduce the size and adopted the drain to source transformer feedback techniques to flatted the gain. The proposed LNA achieves a gain of 11.56 dB over a 3-dB bandwidth from 4.9 to 11.7 GHz with a minimum noise figure (NF) of 3.5 dB. The measured P1dB is -12 dBm and the IIP3 is -1.9 dBm. The power consumption of the LNA is 8.7 mW. The chip size is 0.73 × 0.68 mm2.

The third circuit is a low-power and wideband direct conversion receiver. The receiver circuit consists of a wideband low noise amplifier, unbalanced to balanced transformation transformer and wideband current-driven passive mixer and intermediate frequency (IF) amplifier. To improve NF and power consumption performance of the first design circuit, we redesign the low noise amplifier. An inductively coupled resonator were used in the unbalanced to unbalanced transformation transformer design. This approach reduces the size of passive component and achieves wideband performance without consuming DC power. The proposed receiver achieves a voltage conversion gain of 30.03 dB over 4.5 to 11.7 GHz and minimum double-sideband NF of 9.2 dB. The measured P1dB is -21 dBm and the IIP3 is -14.3 dBm. The measured IIP2 is 35.7 dBm. The power consumption of the receiver is 10.96 mW with the supply voltage 1.8 V. The chip size is 2.38 × 0.94 mm2.

關鍵字(中)

★ 接收機
★ 低雜訊放大器
★ 寬頻

關鍵字(英)

★ receiver
★ low noise amplifer
★ wideband

論文目次

摘要 i
Abstract ii
誌謝 iv
目錄 v
圖目錄 vi
表目錄 ix
第一章緒論 1
1-1 研究動機 1
1-2 研究貢獻 2
1-3 章節介紹 2
第二章應用於X頻段之寬頻低雜訊放大器 3
2-1 三級串聯結合變壓器回授之低雜訊放大器架構與分析 3
2-1-1 電路模擬與量測結果 13
2-1-2 結果與討論 20
2-2 反向放大架構結合電阻回授之低雜訊放大器架構與分析 22
2-2-1 電路模擬與量測結果 27
2-2-2 結果與討論 32
第三章應用於C/X頻段的低功耗寬頻前端電路接收機 34
3-1 前言 34
3-2 寬頻低雜訊放大器分析與設計 36
3-3 電流模態被動混波器分析與設計 44
3-4 平衡與不平衡轉換變壓器分析與設計 49
3-5 電路模擬與量測結果 52
3-6 結果與討論 61
第四章結論 63
4-1 結論 63
4-2 未來方向 64
參考文獻 65

參考文獻

[1] Amitabha Ghosh, “Can mm wave wireless technology meet the future capacity crunch” ,invited speaking in IEEE International Conference on Communications (ICC), Budapest, Hungary, 9-13 Jun. 2013.
[2] Wonil Roh, “Performances and feasibility of mm wave beamforming prototype for 5G cellular communications”, invited talk in IEEE International Conference on Communications (ICC), Budapest, Hungary, 9-13 Jun. 2013.
[3] Yoshihisa Kishiyama, “Future radio access for 5G”, invited talk in The International Workshop on Cloud Cooperated Heterogeneous Networks, Osaka, Japan, 23 Oct., 2013.
[4] David J. Cassan, John R. Long, “A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-μm CMOS,” IEEE J. Solid State Circuits, vol. 38, no. 3, pp. 427-435, Mar. 2003.
[5] D. J. Allstot, X. Li, and S. Shekhar, “Design considerations for CMOS low-noise amplifiers,” in Proc. IEEE Radio Freq. Integr. Circuit Symp., 2004, pp. 97-100.
[6] T. Yao, M. Q. Gordon, K. K. W. Tang, K. H. K. Yau, M.-T. Yang, P. Schvan, and S. P. Voinigescu, “Algorithmic design of CMOS LNAs and Pas for 60-GHz radio,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1044-1057, Aug. 2004.
[7] C.-H Li, C.-N Kuo, and M.-C Kuo, “A 1.2-V 5.2-mW 20-30-GHz wideband receiver front-end in 0.18-μm CMOS,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 11, pp. 3502-3512, Nov. 2012.
[8] Y.-T. Lo and J.-F. Kiang, “Design of wideband LNAs using parallel-to-series resonant matching network between common-gate and common-source stages,” IEEE Trans. Microw. Theory Techn., vol. 59, no. 9, pp. 2285-2294, Sep. 2011.

[9] M. Khurram and S. M. R. Hasan, “Series peaked noise matched g_m-boosted 3.1-10.6 GHz CG CMOS differential LNA for UWB WiMedia,” Electron. Lett., vol. 47, no. 24, pp. 1346-1348, Nov. 2011.
[10] R. M. Weng, C. Y. Liu, and P. C. Lin, “A low-power full-band low-noise amplifier for ultra-wideband receivers,” IEEE Trans. Microw. Theory. Techn., vol. 58, no. 8, pp. 2077-2083, Aug. 2010.
[11] Y. S. Lin, C. Z. Chen, H. Y. Yang, C. C. Che, J. H. Lee, G.W. Huang, and S. S. Lu, “Analysis and design of a CMOS UWB LNA with dual-RLC-branch wideband input matching network,” IEEE Trans. Microw. Theory. Techn., vol. 57, no. 2, pp. 287-296, Feb. 2010.
[12] B. Razavi, RF Microelectronics, 2^nded, Prentice Hall, 2011.
[13] Y.-S Lin, C.-C Wang, G.-L Lee, C.-C Chen, ”High-performance wideband low-noise amplifier using enhanced π–match input network,” IEEE Microw. Wireless Compon. Lett., vol. 24, no. 3, pp. 200-202, Mar. 2014
[14] N. Poobuapheun, C. Wei-Hung, Z. Boos, and A. Niknejad, “A 1.5-V 0.7-2.5-GHz CMOS quadrature demodulator for multiband direct-conversion receivers,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1669-1677, Aug. 2007.
[15] V. H. Le, H. N. Nguyen, I. Y. Lee, S. K. Han, and S. G. Lee, “A passive mixer for a wideband TV tuner,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 7, pp.398-401, Jun. 2011.
[16] M. Valla et al., “A 72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 970-977, Apr. 2005.
[17] S. Zhou and M.-C. F. Chang, “A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1084-1093, May. 2005.
[18] J.-H. C. Zhan, B. R. Carlton, and S. S. Taylor, “ A broadband low-cost direct-conversion receiver front-end in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp.1132-1137, May. 2008.
[19] K. Jusung and J. Silva-Martinez, “Low-power, low-cost CMOS direct-conversion receiver front-end for multistandard applications,” IEEE J. Solid-State Circuits, vol. 48, no. 9, pp. 2090-2103, 2013.
[20] S. Lee, J. Bergervoet, K. S. Harish, D. Leenaerts, R. Roovers, R. v. d. Beek, and G. v. d. Weide, “A broadband receive chain in 65 nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 418-612.
[21] 簡菁儀, "應用於 K頻段射頻接收機之寬頻低功耗CMOS低雜訊放大器," 碩士論文,電機工程學系, 國立中央大學, 民國 103 年.
[22] 李忠穎, "應用於 5-11 GHz寬頻低雜訊與5 GHz /11 GHz雙頻低雜訊放大器之研製," 碩士論文, 電機工程學系, 國立中央大學, 民國 104 年.

指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2016-8-11

推文