直線偵測硬體加速器設計與實作

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姓名

郭旻灝(MIN-HAO GUO) 查詢紙本館藏

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資訊工程學系

論文名稱

直線偵測硬體加速器設計與實作
(Design and Implementation of Hardware Accelerator for Line Detection)

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摘要(中)

由於直線偵測演算法需要一連串循序、復雜的影像處理流程，因此在軟體實現的時候需要利用高效能的處理器來降低計算的處理時間。本論文利用MIAT(本實驗室)系統方法論，設計一個平行化運算的直線偵測硬體加速器。此加速器架構包含一個上層的管線化控制器，用來控制底下Canny邊緣偵測模組以及Hough Transform模組的運作，利用邊緣偵測模組得到的影像邊緣資訊進行Hough Transform以提高直線偵測結果的準確度，再利用管線化控制的方式來提升各模組的效能。本研究根據Canny的流程使用高斯模糊處理降低雜訊造成的錯誤邊緣偵測，並且在不影響直線偵測結果的前提下，減少運算次數及資源使用量，用以提升系統效能，相較於Xu與Chen的方式分別降低了84％與74％的電路資源使用。利用方法論生成之硬體功能電路，具備好的分散式架構以及可擴充性，使其更容易應用在各式嵌入式系統中。

摘要(英)

Due to line detection algorithm require a series of sequential complex image processing. Therefore, implementing line detection algorithm with software usually needs high-efficiency processor to reduce the processing time. In this paper, MIAT system design methodology is used to design a parallel calculating line detection hardware accelerators. Architecture of the accelerator contains a top layer pipeline controller to control Canny edge detection module and Hough Transform module below. Hough Transform module use the information from edge detection module to enhance accuracy. And pipeline control is used to improve efficacy of each module. According to Canny’s method we used Gaussian blur processing to reduce wrong edge detection cause by noise. In the case does not affect the line detection result we reducing the number of operations and the amount of resources to Enhance system performance. Compared to Chen’s research and Xu’ research our method reduce 84％ and 74％ circuit resource. Hardware circuits generate by methodology, with good distributed architecture and scalability, making it easier to use in a variety of embedded systems.

關鍵字(中)

★ 邊緣偵測
★ 硬體加速器
★ 直線偵測

關鍵字(英)

★ Hough Transform
★ Edge Detection
★ FPGA

論文目次

摘要 I
ABSTRACT II
誌謝 III
目錄 IV
圖目錄 VI
表目錄 X
第一章、緒論 1
1.1 研究背景 1
1.2 研究目的 3
1.3 論文架構 3
第二章、文獻回顧 4
2.1 邊緣偵測 4
2.2 Canny 邊緣偵測演算法 6
2.2.1 高斯濾波器 6
2.2.2 計算影像梯度強度與方向 8
2.2.3 非最大值抑制與Hysteresis thresholding 8
2.3 Canny邊緣偵測硬體架構 11
2.4 Hough Transform 13
2.5 Hough Transform 硬體加速架構 16
第三章、直線偵測硬體加速器設計 18
3.1 嵌入式系統設計方法論 18
3.1.1 IDEF0系統架構 19
3.1.2 Grafcet離散事件建模 21
3.2 系統架構 26
3.3 離散事件建模 28
3.4 邊緣偵測模組硬體合成 37
3.4.1 高斯濾波模組 38
3.4.2 梯度計算模組 39
3.4.3 非最大抑制模組 41
3.4.4 滯後閥值模組 42
3.5 Hough Transform模組 44
3.6 管線控制器設計 45
第四章、系統驗證與分析 49
4.1 實驗平台 49
4.2 CMOS取像控制 51
4.3 Canny邊緣偵測實驗 52
4.4 hough轉換偵測實驗 55
4.5 比較分析 57
第五章結論與未來研究方向 59
5.1 結論 59
5.2 未來研究方向 60
參考文獻 61

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指導教授

陳慶瀚

審核日期

2016-1-27

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