形態學影像處理硬體加速器設計與應用

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姓名

羅鳴雁(Ming-yan Luo) 查詢紙本館藏

畢業系所

資訊工程學系

論文名稱

形態學影像處理硬體加速器設計與應用
(Design and Application of Morphological Image Processing Hardware Accelerator)

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摘要(中)

大多數形態學研究都強調硬體加速器，一旦需求改變或設計變更時，須重新設計硬體架構。本論文以MIAT(本實驗室)系統方法論，設計一個高彈性、可程式化的形態學影像處理硬體加速器架構。此架構包含多個串連的形態學核心模組(Mathematical Morphology Function Block, MMFB)，以管線化控制提升各模組的效能。藉由軟體控制其硬體表現行為，達到高度彈性化且通用性之硬體加速器。在功能驗證中以條碼辨識為例，使用本硬體架構將影像侵蝕，刪除不必要之資訊，在使用膨脹運算還原回原始影像資料，最後經辨識得到其結果。本研究的貢獻在於軟硬體整合，以軟體控制其硬體表現行為，且經功能驗證後，其硬體架構可提供高彈性化及通用性。

摘要(英)

Most researches put emphasis on the hardware accelerator for mathematical morphology. If there is something wrong, the architecture will need to be redesigned. In this paper, MIAT (our laboratory) system methodology is used to design a high flexible and programmable morphological hardware accelerator. There are several morphology models (Mathematical Morphology Function Block) inside and pipeline control is used to improve each MMFB’s efficacy. We use software to control its hardware performance. By these means, it can achieve high flexibility and general purpose. We use barcode identification to verify this architecture. Noise is deleted with erosion operator and the origin image information is got by dilation. Finally, get the result with identification. The contribution of this paper is to integrate hardware and software. Control the hardware performance behavior with software. After functional verification, the hardware architecture provides high elasticity and general purpose.

關鍵字(中)

★ 形態學
★ 影像處理
★ 硬體加速器

關鍵字(英)

★ Morphological Image Processing
★ Hardware Accelerator

論文目次

摘要 I
ABSTRACT II
目錄 . III
圖目錄 V
表目錄 VIII
第一章、緒論 1
1.1 研究背景 1
1.2 研究目的 2
1.3 論文架構 3
第二章、形態學影像處理硬體架構 4
2.1 形態學基本運算 4
2.1.1 侵蝕 5
2.1.2 膨脹 6
2.1.3 斷開 7
2.1.4 閉合 7
2.2 形態學影像處理器 8
2.3 線性收縮式陣列(Linear Systolic Array) 11
2.4 Pseudo-MIMD 12
2.5 SE 分解 13
2.6 可重組形態學硬體加速器 14
第三章、形態學影像處理軟硬體整合設計 18
3.1 MIAT 系統設計方法論 18
3.2 軟硬體整合設計 22
3.3 MMFB 設計與實作 23
3.3.1 MMFB 架構 23
3.3.2 MMFB 遮罩運算 24
3.3.3 彈性控制器架構 26
3.4 Mask operation 遮罩運算 27
3.4.1 Sobel Operator 27
3.4.2 相鄰像素平均法(Neighborhood averaging) 28
3.5 管線化控制器(Pipeline Controller) 29
第四章、條碼辨識系統軟硬體整合設計與驗證 32
4.1 軟硬體開發環境 32
4.1.1 CMOS 影像感測器 32
4.1.2 FPGA 33
4.1.3 STM32F429 34
4.2 一維條碼辨識原理與演算法 35
4.3 條碼辨識系統設計 36
4.3.1 IDEF0 系統架構 37
4.4 系統合成 41
4.4.1 嵌入式硬體合成 41
4.4.2 軟硬體整合 44
4.5 結果與討論 45
4.5.1 執行時間 45
4.5.2 執行成果 45
第五張、結論與未來研究方向 48
5.1 結論 48
5.2 未來研究方向 48
參考文獻 49

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指導教授

陳慶瀚

審核日期

2015-12-21

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