博碩士論文 102522069 詳細資訊




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姓名 謝昀宸(Yun-chen Hsieh)  查詢紙本館藏   畢業系所 資訊工程學系
論文名稱 迎向物聯網:支援語音辨識開發之可客製化數位訊號處理組譯器設計
(Toward Internet of Things: A Customizable DSP assembler for Speech Recognition Programming)
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摘要(中) 近年來,物聯網為網路發展的趨勢之一,舉凡穿戴式裝置、智慧家庭至智慧城市等,均是現今熱門議題,隨之而來大量的多媒體訊號處理、影像及語音辨識等相關應用,目前的行動裝置及多媒體產品,通常透過數位訊號處理器(DSP)為特定應用,設計演算法處理即時數位訊號。 DSP晶片開發商會提供部分可客製化介面,給予系統應用開發商可客製化其DSP之指令集的彈性,使得演算法達到低功耗及高效能之目的,但同時也產生出許多的軟體開發上的問題,由於不同的DSP晶片會對應不同的組譯器及模擬器,因此DSP開發時通常會採用晶片開發商所授權之整合開發環境(IDE),對於系統應用開發商或是中小型開發者而言,IDE對於客製化DSP指令集的支援是極為重要,而既有的IDE通常為授權且封閉的環境,無法對於其組譯器及模擬器進行修改,無法達到驗證及模擬客製化DSP指令集,對於軟體開發上相當不利。 因此在這篇論文中我們提出了一彈性組譯器架構,來達到彈性擴充客製化指令集和模擬之目的,在客製化DSP指令集的軟體開發上,提供快速驗證及模擬的特性,除此之外,我們同時實作ADSP-218x DSP完整指令集以及DSP預處理器,作為驗證系統的正確性及完整性。
摘要(英) Recently, Internet of Things is one of the technology trends in the world. Nowadays, wearable devices, smart home, smart city, etc., is hot issue for application and research. Consequently, multimedia applications get more popular like video analysis, speech recognition, etc., These are used to using Digital Signal Processor (DSP) to design the algorithm for specific application, which processes the real-time digital signals. The DSP chip vendor provides the interfaces of customized for application development companies, which can specify their own instruction for specific algorithm to optimize the performance and power consumption. Although it brings numerous benefits, it introduces an additional software development problem. Most of the DSP development environment is always using the DSP vendor’s Integrated Development Environment (IDE). The licensed and closed platform IDE becomes a drawback in software development, which the IDE cannot support the application specific instruction-set, especially in the coding validation and simulation. In this paper, we propose a flexible assembler architecture to meet the requirement of extension instructions and the simulation. Moreover, we implemented the preprocessor and the native ADSP-218x instruction-set in a comprehensive validation.
關鍵字(中) ★ 物聯網
★ 語音辨識
★ 數位訊號處理
★ 特殊應用指令集
★ 組合語言
★ 組譯器
★ 整合型開發環境
關鍵字(英) ★ Internet of Things
★ Speech Recognition
★ Digital Signal Processing
★ Application Specific Instruction-set
★ Assembler
★ Integrated Development Environment
論文目次 中文摘要 ii
Abstract iii
Acknowledgement iv
1. Introduction 1
2. Background and Related Work 5
2.1 Digital Signal Processing 5
2.2 ASIP and Development environment effective 7
2.3 Architecture Description Language (ADL) 9
2.3.1 Behavior ADLs, ISDL and nML 11
2.3.2 Mixed ADLs, EXPRESSION and LISA 15
2.3.3 Summary comparison of ADL-based solutions 19
2.4 VisualDSP++, the vendor’s IDE 21
3. System Design 22
3.1 System architecture 22
3.2 Preprocessor features and architecture 24
3.3 Assembler keywords, directives and architecture 30
3.4 The operator priority of instructions 34
3.5 Instruction-set architecture 35
4. Implementation and Validation 37
4.1 Implementation overview 37
4.2 Preprocessor module 38
4.3 Assembler module 41
4.3.1 Assembler directive module 44
4.3.2 Instruction-set module 48
4.4 Simulator module 52
4.5 System validation 53
5. Conclusion 55
參考文獻 [1] J. Gubbi, R. Buyya, S. Marusic and M. Palaniswami, "Internet of Things (IoT): A vision, architectural elements, and future directions," Future Generation Comput.Syst., pp. 1645-1660, 29 7 2013.
[2] IBM, "IBM model for the Internet of Things," IBM X-Force Research and Development, [Online]. Available: http://www-03.ibm.com/security/resources/index.html.
[3] S. H. Park, S. H. Won, J. B. Lee and S. W. Kim, "Smart home–digitally engineered domestic life," Personal and Ubiquitous Computing, pp. 189-196, 7 3-4 2003.
[4] A. P. M. David Steele and F. P. M. Rudan Bettelheim, "Voice and IP Audio Enabled IoT Applications," [Online]. Available: http://www.arcturusnetworks.com/whitepapers/Developing_Voice_Audio_IoT_Applicaitons__WP_v0-1-1.pdf.
[5] Freescale, "Embedded VoIP for Commercial and Industrial Applications," 2008. [Online]. Available: http://www.arcturusnetworks.com/whitepapers/MSG-15389-VoIP-WP-v3HR.pdf.
[6] D. Skolnick and N. Levine, "Why Use DSP?," Analog Devices: Analog Dialogue: Digital Signal Processing 101 An Introductory Course in DSP System Design, vol. 1, pp. 31-31, 1997.
[7] McClellan, J. H., R. W. Schafer and M. A. Yoder, "Signal processing first," Pearson/Prentice Hall, 2003.
[8] Y. H. Ha, "Digital signal processing".2009.
[9] M. J. Wirthlin and B. L. Hutchings, "A dynamic instruction set computer," FPGAs for Custom Computing Machines, 1995. Proceedings. IEEE Symposium on, pp. 99-107, 1995.
[10] D. E. Thomas and P. R. Moorby, The Verilog® Hardware Description Language, Springer Science & Business Media, 2002.
[11] C. Galuzzi and K. Bertels, "The instruction-set extension problem: A survey," Springer, pp. 209-220, 2008.
[12] G. Hadjiyiannis, S. Hanono and S. Devadas, "ISDL: An instruction set description language for retargetability," Proceedings of the 34th annual Design Automation Conference, ACM, pp. 299-302, 1997.
[13] J. Van Praet, D. Lanneer, W. Geurts and G. Goossens, "nML: A structural processor modeling language for retargetable compilation and ASIP design," Processor Description Languages, Morgan Kaufmann, p. 65, 2011.
[14] A. Fauth, J. Van Praet and M. Freericks, "Describing instruction set processors using nML," European Design and Test Conference, 1995. ED&TC 1995, Proceedings. IEEE, pp. 503-507, 1995.
[15] A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt and A. Nicolau, "EXPRESSION: A language for architecture exploration through compiler/simulator retargetability," Design, Automation, and Test in Europe, Springer, pp. 31-45, 2008.
[16] A. Hoffmann, O. Schliebusch, A. Nohl, G. Braun, O. Wahlen and H. Meyr, "A methodology for the design of application specific instruction set processors (ASIP) using the machine description language LISA," Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, pp. 625-630, 2001.
[17] L. Taglietti, O. C. José Filho, D. C. Casarotto, O. J. Furtado and L. C. dos Santos, "Automatically retargetable pre-processor and assembler generation for asips," IEEE-NEWCAS Conference, 2005. The 3rd International, pp. 215-218, 2005.
[18] J. Cong, M. A. Ghodrat, M. Gill, H. Huang, B. Liu, R. Prabhakar, G. Reinman and M. Vitanza, "Compilation and architecture support for customized vector instruction extension," Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, pp. 652-657, 2012.
[19] K.-S. Lin, G. A. Frantz and J. Ray Simar, "The TMS320 Family of Digital Signal Processors," Texas Instruments, 1997. [Online]. Available: http://www.ti.com/lit/an/spra396/spra396.pdf.
[20] "ADSP 21xx Processors: Manuals," Analog Devices, [Online]. Available: http://www.analog.com/en/products/landing-pages/001/adsp-manuals.html.
[21] "Considerations for Selecting a DSP Processor—Why Buy the ADSP-2181? (The Analog Devices ADSP-2181 vs. Texas Instruments & Motorola Fixed-Point DSPs)," Analog Devices. [Online].
[22] Moore and Gordon, "No exponential is forever–but we can delay forever.," in IBM Academy of Technology Annual Meeting, San Francisco, CA, 2003.
[23] M. Adiletta, M. Rosenbluth, D. Bernstein, G. Wolrich and H. Wilkinson, "The next generation of Intel IXP network processors," Intel technology journal, pp. 6-18, 6 3 2002.
[24] "MPC8280 PowerQUICC? II Family Reference Manual," Semiconductor, Freescale, 2005.
[25] R. Leupers, K. Karuri, S. Kraemer and M. Pandey, "A design flow for configurable embedded processors based on optimized instruction set extension synthesis," Design, Automation and Test in Europe Proceedings. Vol. 1. IEEE, 1 6 2006.
[26] P. C. Clements, "A survey of architecture description languages," Proceedings of the 8th international workshop on software specification and design IEEE Computer Society, 1996.
[27] P. Mishra and N. Dutt, "Architecture description languages for programmable embedded systems," IEE Proceedings-Computers and Digital Techniques, pp. 285-297, 2005.
[28] M. Freericks, "The nML machine description formalism".1991.
[29] A. Devices, "VisualDSP Development Software," VisualDSP Development Software, 2012.
[30] A. Devices, "VisualDSP 3.1, C/C Compiler and Library Manual for Blackfin Processors," VisualDSP Development Software, 2003.
[31] A. Devices, "Analog Devices VisualDSP++," Analog Devices, [Online]. Available: http://www.analog.com/en/design-center/processors-and-dsp/evaluation-and-development-software/vdsp-bf-sh-ts.html#dsp-overview.
[32] P. Number, "VisualDSP++ 5.0 Assembler and Preprocessor Manual," Assembler and Preprocessor Manual, 2010.
[33] A. Devices, "ADSP-218x DSP instrruction-set reference," Analog Devices, 2004.
[34] Z. Szűgyi, Á. Sinkovics, N. Pataki and Z. Porkoláb, "C metastring library and its applications," in Generative and Transformational Techniques in Software Engineering III, Springer.
[35] H. Kaiser, "Boost Wave: a Standard conformant C++ preprocessor library," 10 1 2004. [Online]. Available: http://www.codeproject.com/Articles/3853/Wave-a-Standard-conformant-C-preprocessor-library.
指導教授 吳曉光(Hsiao-kuang Wu) 審核日期 2015-7-14
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