具電容放大技術和自適應迴路增益控制器之5 Gbps雙路徑時脈與資料回復電路

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姓名

鄭柏旻(Po-Min Cheng) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具電容放大技術和自適應迴路增益控制器之5 Gbps雙路徑時脈與資料回復電路
(A 5 Gbps Dual Path Clock and Data Recovery with Capacitor-Amplified Technique and Adaptive Loop Gain Controller)

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摘要(中)

隨著半導體產業和電腦相關產業的快速發展，且高速串列傳輸系統也廣泛被使用，所以資料的傳遞速度日漸提升。在高速串列傳輸系統中，時脈與資料回復電路扮演了還原時脈和輸入資料時序上的問題，也因為資料速率的增加，電路的時間容忍區間會變得非常小，難以確保時脈與資料回復電路有好的誤碼率和抖動容忍度，所以如何降低資料上誤碼率的發生是現今必須克服的問題。
本論文將參考USB 3.0規範並提出一個具自適應迴路增益控制器和數位式電容放大技術之雙路徑時脈與資料回復電路，透過自適應迴路增益控制器偵測輸入抖動之頻率資訊來調整系統迴路增益，可優化系統的產生的抖動和抖動容忍度，改善了50 %的低頻抖動容忍度和12 %高頻抖動容忍度。數位式電容放大器去累積二進位相位偵測器之輸出訊號，因此使用的電容值從205 pF減少到3.2 pF，所以減少了50 %的面積成本並且可維持原有的系統穩定度。本論文使用90 nm標準CMOS製程來實現，電路操作電壓為1 V，晶片面積為0.073 mm2，輸入資料速率為5 Gbps時，還原時脈的峰對峰值抖動為26.4 pspp，和方均根值抖動為3.2 psrms，消耗功率為16.8 mW。

摘要(英)

As CMOS technology continues to advance, the computing capabilities of integrated circuits are expanding, and the fast serial link technologies have received significant attention in the recent past. The clock and data recovery (CDR) is the crucial role of receiver timing circuits in the serial link systems, and achieves to optimally sample the input data with various timing jitter profiles. Due to increasing of the data rate, the timing budget of the CDR becomes very tight and makes it more difficult to guarantee the required Bit-Error-Rate (BER) and the jitter tolerance (JTOL).
This study takes USB 3.0 specification as reference material, and presents a dual path clock and data recovery with adaptive loop gain controller (ALGC) and capacitor-amplified technique (CA). The ALGC enhances the jitter performance and JTOL by detecting the jitter frequency spectrum and controlling loop gain adaptively, and the enhanced percentage of low and high frequency input jitter is about 50% and 12%, respectively. To reduce the area of loop filter, the CA is utilized in the integral path to count the output signal of the bang-bang phase detector, and the reduced percentage of area is about 50% without lowering system stability. The test chip was fabricated by a 90-nm standard CMOS process with a 1-V supply and the core area occupies 0.073 mm2. The measured jitter of the recovered clock is 3.2 psrms and 26.4 pspp, and the power consumption is 16.8 mW at the 5-Gbps data rate.

關鍵字(中)

★ 時脈與資料回復電路
★ 電容放大技術
★ 自適應迴路增益控制器

關鍵字(英)

★ Clock and Data Recovery
★ Capacitor-amplified Technique
★ Adaptive Loop Gain Controller

論文目次

摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 viii
表目錄 xii
第1章緒論 1
1.1 研究動機 1
1.2 論文架構 4
第2章高速串列傳輸之訊號完整性 5
2.1 基本觀念 5
2.1.1 資料類型 5
2.1.2 隨機二元資料的特性 6
2.1.3 資料編排形式 7
2.2 時脈抖動簡介 8
2.2.1 隨機性抖動(Random Jitter, RJ) 9
2.2.2 定量性抖動(Deterministic Jitter, DJ) 10
2.2.2.1 資料相關抖動(DDJ) 10
2.2.2.2 責任週期失真(DCD) 11
2.2.2.3 週期性抖動(PJ) 12
2.3 抖動量測的方法 13
2.3.1 時間間隔誤差(Time Interval Error, TIE) 13
2.3.2 週期抖動 14
2.3.3 循環抖動 15
2.3.4 抖動量測方式之總結 16
2.4 眼圖分析 17
2.5 誤碼率 18
第3章時脈與資料回復電路之背景簡介 21
3.1 時脈與資料回復電路簡介 21
3.1.1 相位偵測器類型 22
3.1.2 取樣速率 23
3.1.3 抖動容忍度 24
3.1.4 抖動轉移函數 25
3.2 傳統時脈與資料回復電路 26
3.2.1 鎖相迴路式時脈與資料回復電路 26
3.2.2 混合鎖相迴路/延遲鎖相迴路式時脈與資料回復電路 27
3.2.3 超取樣式時脈與資料回復電路 28
3.2.4 相位選擇式時脈與資料回復電路 29
3.2.5 雙路徑式時脈與資料回復電路 30
3.3 提高抖動容忍度之設計背景 31
3.3.1 多增益路徑之超取樣式時脈與資料回復電路 31
3.3.2 自適應比例項增益控制之時脈與資料回復電路 33
3.3.3 自適應迴路增益控制之時脈與資料回復電路 34
3.4 比較與討論 35
第4章具電容放大技巧與自適應迴路增益控制器之時脈與資料回復電路設計 37
4.1 電路架構 37
4.2 操作說明 39
4.2.1 自適應迴路增益控制器 40
4.2.2 電容放大技術 42
4.3 系統分析 44
4.3.1 鎖相迴路系統分析 44
4.3.2 非線性時脈與資料回復電路系統分析 47
4.3.3 非線性時脈與資料回復電路之非理想現象 52
4.3.3.1 迴路延遲之影響 52
4.3.3.2 領先和落後比例項增益匹配誤差之影響 53
4.3.3.3 領先和落後積分項增益匹配誤差之影響 55
4.4 行為模擬 56
4.5 子電路介紹 58
4.5.1 自適應迴路控制器 58
4.5.2 數位式電容放大器 62
4.5.3 迴路濾波器 62
4.5.4 半速率二進位相位偵測器 64
4.5.5 電壓電流轉換器 67
4.5.6 電流幫浦 68
4.5.7 雙輸入壓控振盪器 70
4.5.8 相位頻率偵測器 72
4.5.9 除頻器 73
4.5.10 擺幅轉換電路 74
4.6 模擬結果 74
4.6.1 佈局前模擬 75
4.6.2 佈局後模擬 77
4.6.3 抖動容忍度模擬 79
第5章晶片佈局與量測 81
5.1 電路佈局 81
5.1.1 晶片封裝 82
5.1.2 佈局與電源規劃 84
5.2 量測考量 85
5.2.1 量測環境 85
5.2.2 印刷電路板 86
5.2.3 高頻輸出緩衝器 87
5.2.4 低頻輸出緩衝器 88
5.2.5 高頻輸入端 89
5.3 晶片與印刷電路板照相 91
5.4 量測結果 92
5.4.1 頻率資訊鎖相迴路量測 92
5.4.2 相位資訊資料回復迴路量測 93
5.4.3 抖動容忍度測試 97
5.5 規格比較表 99
第6章結論 101
6.1 結論 101
6.2 未來研究方向-自適應迴路增益控制器-多增益式調整 101
參考文獻 102

參考文獻

[1] PCI Express® Base Specification, Revision 2.1, PCI-SIG, 2010.
[2] Serial ATA International Organization, Serial ATA Revision 3.0, SATA-IO, 2009.
[3] Universal Serial Bus Specification, Revision 3.1, USB-IO, 2013
[4] B. Razavi, “Design of Integrated Circuits for Optical Communications,” McGraw-Hill, 2003.
[5] 吳彥學, “應用於PCI Express Generation II之5-Gb/s無電感式類比等化器的式計與實現,” 碩士論文, 國立中央大學, 2009.
[6] A. X. Widmer, and P. A. Franaszek, ”A DC-balanced, partitioned-block, 8b/10b reansmission code,” IBM J. Res and Develop., vol. 27, pp. 440–451, Sep. 1983.
[7] Tektronix, “數位示波器的應用抖動(jitter)測量”.
[8] SHF Communication Technologies AG, “Application note AN-jitter-1-jitter analysis using SHF 10000 series bit error rate testers,” 2005.
[9] Agilent Technologies, “Measuring jitter in digital systems,” Application Note 1448-1.
[10] L. Luo, J. Wilson, S. Mick, J. Xu, L. Zhang, E. Erickson, and P. Franzon, “A 36 Gb/s ACCI mutli-channel bus using a fully differential pulse receiver,” in Proc. IEEE Custom Integrated Circuits Conf., pp. 773–776, Sep. 2006.
[11] Maxim, “Choosing AC-coupling capacitors,” Application Note: HFAN-1.1, 2000.
[12] Agilent Technologies, “Finding sources of jitter with real-time jitter analysis,” 2008.
[13] STMicroelectronics, “Improving a jitter definition,” 2007.
[14] Tektronix, “Understanding and characterizing timing jitter”.
[15] Altera Corporation, “Deterministic jitter (DJ) definition and measurement,” 2009.
[16] Maxim, “Optical receiver performance evaluation”.
[17] Maxim, “NRZ bandwidth - HF cutoff vs. SNR,” Application Note: HFAN-09.0.1.
[18] H. J. Jeon, R. Kulkarni, Y. C. Lo, J. Kim, and S. M. Jose, “A bang-bang clock and data recovery using mixed mode adaptive loop gain strategy,” IEEE J. Solid-State Circuits, vol. 48, no. 6, pp. 1398–1415, Jun. 2013.
[19] K. S. Kwak, and O. K. Kwon, “Power-reduction technique Using a single edge-tracking clock for multiphase clock and data recovery circuit,”IEEE Trans. Circuits Syst. II, Express Briefs, vol. 61, no. 4, pp. 239–243, Apr. 2014.
[20] J. H. Yoon, S. W. Kwon, and H. M. Bae, “A DC-to-12.5 Gb/s 9.76 mW/Gb/s all-rate CDR with a single LC VCO in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 52, no. 3, pp. 856–866, March 2017.
[21] S. Byun, “A 400 Mb/s~2.5 Gb/s referenceless CDR IC using intrinsic frequency detection capability of half rate linear phase detector,” IEEE Trans. Circuits Syst. I, Regular Papers, vol. 63, no. 10, pp. 1592–1604, Oct. 2016.
[22] D. Dalton, K. Chai, E. Evans, M. Ferriss, D. Hitchcox, P. Murray, S. Selvanayagam, P. Shepherd, and L. DeVito, “12.5-Mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2713–2725, Dec. 2005.
[23] X. Maillard, F. Devisch, and M. Kuijk, “A 900-Mb/s CMOS data recovery DLL using half-frequency clock,” IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 711–715, Jun. 2002.
[24] J. Kim and D. K. Jeong, “Multi-gigabit-rate clock and data recovery based on blind oversampling,” IEEE Commun. Mag., vol. 41, pp. 68–74, Dec. 2003.
[25] M. Nogawa, K. Nishimura, S. Kimura, T. Yoshida, T. Kawamura, M. Togashi, K. Kumozaki, and Y. Ohtomo, “A 10Gb/s burst-mode CDR IC in 0.13um CMOS,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, pp. 228–229, Feb. 2005.
[26] W. Yin, R. Inti, A. Elshazly, M. Talegaonkar, B. Young and P. K. Hanumolu, “A TDC-less 7 mw 2.5 Gb/s digital CDR with linear loop dynamics and offset-free data recovery,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 3163–3173, Dec. 2011.
[27] M. Brownlee, P. K. Hanumolu, and U. K. Moon, “A 3.2 Gb/s oversampling CDR with improved jitter tolerance,” in Proc. IEEE Custom Integr. Circuits Conf., pp. 353–356, 2007.
[28] D. H. Kwon, Y. S. Park, and W. Y. Choi, “A clock and data recovery circuit with programmable multi-level phase detector characteristics and a built-in jitter monitor,” IEEE Trans. Circuits Syst. I, Regular Papers, vol. 62, no. 6, pp. 1472–1480, June 2015.
[29] C. Sanchez-Azqueta, C. Gimeno, C. Aldea, S. Celma, and C. Azcona, “CMOS receiver with equalizer and CDR for short-reach optical communications,” in Proc. IEEE Int. Symp. Circuits Syst., pp. 497–500, May 2013.
[30] Y. L. Lee, S. J. Chang, R. S. Chu, Y. Z. Lin, Y. C. Chen, G. J. Ren, and C. M. Huang, “A 5 Gb/s 1/4-rate clock and data recovery circuit using dynamic stepwise bang-bang phase detector,” in Proc. IEEE Asian Solid-State Circuit Conf., pp. 141–144, Nov. 2012.
[31] H. Song, D. S. Kim, D. H. Oh, S. Kim, and D. K. Jeong, “A 1.0–4.0-Gb/s all-digital CDR with 1.0-ps period resolution DCO and adaptive proportional gain control,” IEEE J. Solid-State Circuits, vol. 46, pp. 424–434, Feb. 2011.
[32] 劉深淵, 揚清淵, 鎖相迴路, 滄海書局, 2006.
[33] P. K. Hanumolu, G. Y. Wei, and U. K. Moon, “A wide-tracking range clock and data recovery circuit,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 425–439, Feb. 2008.
[34] B. Nikolic, V. G. Oklobdˇzija, V. Stojanovic, W. Jia, J. K. S. Chiu, and M. M. T. Leung, “Improved sense-amplifier-based Flip-Flop: design and measurements,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876–884, June 2000.
[35] G. Shu, S. Saxena, W. S. Choi, M. Talegaonkar, R. Inti, A. Elshazly, B. Young, and P. K. Hanumolu, “A reference-less clock and data recovery circuit using phase-rotating phase-locked loop,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 1036–1047, Apr. 2014.
[36] T. Lee, Y. H. Kim, and L. S. Kim, “A 5-Gb/s digital clock and data recovery circuit with reduced DCO supply noise sensitivity utilizing coupling network,” IEEE Trans. Very Large Scale Integration Syst., vol. 25, no. 1, pp. 380–384, Jan. 2017.
[37] J. Lee, J. S. Kundert, and B. Razavi, “Analysis and modeling of bang-bang clock and data recovery circuits,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1571–1580, Sep. 2004.
[38] 蔡玉章, “應用於有線傳送接收機之可適應性等化器與時脈同步電路的設計與實現,” 碩士論文, 國立中央大學, 2010.
[39] 洪政亮, “高速有線傳輸系統之時脈產生器關鍵技術,” 碩士論文, 國立中央大學, 2014.
[40] 姜柏阡, “基於無限相位循環補償技術延遲鎖相迴路之6 Gbps時脈與資料回復電路,” 碩士論文, 國立中央大學, 2012.
[41] 陳廷宗, “具自適應增益調整之時脈與資料回復電路,” 碩士論文, 國立中央大學, 2014.
[42] 孫世洋, “以符碼間干擾技術實現自適應等化器之5 Gbps半速率時脈與資料回復電路,” 碩士論文, 國立中央大學, 2015.
[43] B. Razavi, “RF MICROELECTRONICS,” Pearson, 2011.
[44] J. W. Moon, K. C. Choi, and W. Y. Choi, “A 0.4-V, 90 ~ 350-MHz PLL with an active loop-filter charge pump,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 61, no. 5, pp. 319–323, May 2014.

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2017-7-19

推文